09 Oct, 2020
1 commit
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As per hardware documentation, ECx_PMUX has precedence
over SerDes protocol.
For LX2160/LX2162 if DPMACs 17 and 18 are enabled as SGMII
through SerDes protocol but ECx_PMUX configured them as RGMII,
then the ports will be configured as RGMII and not SGMII.Signed-off-by: Razvan Ionut Cirjan
11 Sep, 2020
1 commit
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The next DPMAC was always verified if it is enabled. In case of
DPMAC@6, the DPMAC@7 is verified. As DPMAC@7 is disabled, DPMAC@6 will
be considered disabled and not detected by uboot.Signed-off-by: Grigore Popescu
Signed-off-by: Ioana Ciornei
08 Sep, 2020
1 commit
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LX2162 is LX2160 based SoC, it has same die as of LX2160
with different packaging.LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module,
microSD card, eMMC support, serial console, qspi nor flash, qsgmii,
sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes
interface to support three PCIe gen3 interface.Signed-off-by: Meenakshi Aggarwal
03 Dec, 2019
2 commits
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These functions are CPU-related and do not use driver model. Move them to
cpu_func.hSigned-off-by: Simon Glass
Reviewed-by: Daniel Schwierzeck
Reviewed-by: Tom Rini -
This function belongs in mii.h so move it over.
Signed-off-by: Simon Glass
Reviewed-by: Tom Rini
09 May, 2019
1 commit
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if an error occurs in ldpaa_eth_init, need to free all resources
before returning the error.Threfore, free net_dev before returning from ldpaa_eth_init.
Signed-off-by: Pankaj Bansal
Acked-by: Joe Hershberger
15 Mar, 2019
2 commits
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Fix EC1 and EC2 read from correct offset 26, instead of 25
Signed-off-by: Pramod Kumar
Acked-by: Joe Hershberger
Reviewed-by: Prabhakar Kushwaha -
some dpmacs in armv8a based freescale layerscape SOCs can be
configured via both serdes(sgmii, xfi, xlaui etc) bits and via
EC*_PMUX(rgmii) bits in RCW.
e.g. dpmac 17 and 18 in LX2160A can be configured as SGMII from
serdes bits and as RGMII via EC1_PMUX/EC2_PMUX bits
Now if a dpmac is enabled by serdes bits then it takes precedence
over EC*_PMUX bits. i.e. in LX2160A if we select serdes protocol
that configures dpmac17 as SGMII and set the EC1_PMUX as RGMII,
then the dpmac is SGMII and not RGMII.Therefore, in fsl_rgmii_init function of SOC, we will check if the
dpmac is enabled or not? if it is (fsl_serdes_init has already enabled
the dpmac), then don't enable it.Signed-off-by: Pankaj Bansal
Acked-by: Joe Hershberger
Reviewed-by: Prabhakar Kushwaha
07 Dec, 2018
1 commit
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LX2160A Soc is based on Layerscape Chassis Generation 3.2
architecture with features:
16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC,
2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers,
3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs,
4 TZASC instances, etc.SoC personalites:
LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs
LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUsSigned-off-by: Bao Xiaowei
Signed-off-by: Hou Zhiqiang
Signed-off-by: Meenakshi Aggarwal
Signed-off-by: Vabhav Sharma
Signed-off-by: Sriram Dash
Signed-off-by: Priyanka Jain
Reviewed-by: York Sun
12 Oct, 2018
1 commit
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We need to #ifdef some variables to avoid warning about them being
unused.Fixes: 1a048cd65645 ("driver: net: fsl-mc: Add support of multiple phys for dpmac")
Signed-off-by: Tom Rini
11 Oct, 2018
5 commits
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Till now we have had cases where we had one phy device per dpmac.
Now, with the upcoming products (LX2160AQDS), we have cases, where there
are sometimes two phy devices for one dpmac. One phy for TX lanes and
one phy for RX lanes. to handle such cases, add the support for multiple
phys in ethernet driver. The ethernet link is up if all the phy devices
connected to one dpmac report link up. also the link capabilities are
limited by the weakest phy device.i.e. say if there are two phys for one dpmac. one operates at 10G without
autoneg and other operate at 1G with autoneg. Then the ethernet interface
will operate at 1G without autoneg.Signed-off-by: Pankaj Bansal
Acked-by: Joe Hershberger -
when there is no phy present for a dpmac, a dummy phy device is created.
when we move to multiple phy method, we need to create as many dummy phy
devices.Change this method so that we don't need to create dummy phy devices.
We always report linkup if no phy is present.Signed-off-by: Pankaj Bansal
Acked-by: Joe Hershberger -
if an error occurs during init_phy, we should free the phydev structure
which has been allocated by phy_connect.Signed-off-by: Pankaj Bansal
Acked-by: Joe Hershberger -
The phydev structure is present in both ldpaa_eth_priv and
wriop_dpmac_info. the phydev in wriop_dpmac_info is not being usedAs the phydev is created based on phy_addr and bus members of
wriop_dpmac_info, it is appropriate to keep phydev in wriop_dpmac_info.Also phy_regs is not being used, therefore remove it
Signed-off-by: Pankaj Bansal
Acked-by: Joe Hershberger -
The goto label name is misspelled it should be DPMAC not DPAMC
Signed-off-by: Pankaj Bansal
Acked-by: Joe Hershberger
08 Aug, 2018
1 commit
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The ethernet name should be within the ETH_NAME_LEN, as this
is the buffer space allocated to ethernet name.Otherwise, this causes buffer overflow.
Reported-by: Ioana Ciornei
Signed-off-by: Pankaj Bansal
Reviewed-by: York Sun
09 May, 2018
1 commit
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Updated copyright info for the issues reported after running
check-legal test.Signed-off-by: Yogesh Gaur
Reviewed-by: York Sun
07 May, 2018
1 commit
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When U-Boot started using SPDX tags we were among the early adopters and
there weren't a lot of other examples to borrow from. So we picked the
area of the file that usually had a full license text and replaced it
with an appropriate SPDX-License-Identifier: entry. Since then, the
Linux Kernel has adopted SPDX tags and they place it as the very first
line in a file (except where shebangs are used, then it's second line)
and with slightly different comment styles than us.In part due to community overlap, in part due to better tag visibility
and in part for other minor reasons, switch over to that style.This commit changes all instances where we have a single declared
license in the tag as both the before and after are identical in tag
contents. There's also a few places where I found we did not have a tag
and have introduced one.Signed-off-by: Tom Rini
07 Dec, 2017
1 commit
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Existing MC driver framework is based on MC-9.x.x flib. This patch
migrates MC obj (DPBP, DPNI, DPRC, DPMAC etc) to use latest MC flib
which is MC-10.3.0.Changes introduced due to migration:
1. To get OBJ token, pair of create and open API replaces create APIs
2. Pair of close and destroy APIs replaces destroy APIs
3. For version read, get_version APIs replaces get_attributes APIs
4. dpni_get/reset_statistics APIs replaces dpni_get/set_counter APIs
5. Simplifies struct dpni_cfg and removes dpni_extended_cfg struct
6. Single API dpni_get_buffer_layout/set_buffer_layout replaces
dpni_get_rx/set_rx, tx related, tx_conf_buffer_layout related APIs.
New API takes a queue type as an argument.
7. Similarly dpni_get_queue/set_queue replaces
dpni_get_rx_flow/set_rx_flow , tx_flow related, tx_conf related
APIsSigned-off-by: Yogesh Gaur
Signed-off-by: Priyanka Jain
Reviewed-by: York Sun
15 Nov, 2017
1 commit
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The zero value returned from qbman_swp_acquire() is an error
condition meaning no free buffer for allocation.Signed-off-by: Ashish Kumar
Signed-off-by: Kushwaha Prabhakar
[YS: revised commit message]
Reviewed-by: York Sun
27 Oct, 2017
1 commit
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Since TX delay is now enabled only in PHY_INTERFACE_MODE_RGMII_ID
PHY_INTERFACE_MODE_RGMII_TXID.These change where introduced in phy driver in commit 05b29aa0cb68
("net: phy: realtek: fix enabling of the TX-delay for RTL8211F").Signed-off-by: Ashish Kumar
Reviewed-by: York Sun
11 Sep, 2017
2 commits
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This patch adds support for RGMII protocol
NXP's LDPAA2 support RGMII protocol. LS1088A is the
first Soc supporting both RGMII and SGMII.Signed-off-by: Prabhakar Kushwaha
Signed-off-by: Amrita Kumari
Signed-off-by: Ashish Kumar
Reviewed-by: York Sun -
LS1088A is compliant with the Layerscape Chassis Generation 3 with
eight ARM v8 Cortex-A53 cores in 2 cluster, CCI-400, one 64-bit DDR4
SDRAM memory controller with ECC, Data path acceleration architecture
2.0 (DPAA2), Ethernet interfaces (SGMIIs, RGMIIs, QSGMIIs, XFIs),
QSPI, IFC, PCIe, SATA, USB, SDXC, DUARTs etc.Signed-off-by: Alison Wang
Signed-off-by: Prabhakar Kushwaha
Signed-off-by: Ashish Kumar
Signed-off-by: Raghav Dogra
Signed-off-by: Shaohui Xie
[YS: Revised commit message]
Reviewed-by: York Sun
15 Aug, 2017
1 commit
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Even after memory free of phydev, priv is still pointing to the
obsolete address.
So update priv->phydev as NULL after memory free.Signed-off-by: Prabhakar Kushwaha
Signed-off-by: Ashish Kumar
Acked-by: Joe Hershberger
18 Apr, 2017
1 commit
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Use CONFIG_ARCH_LS2080A instead.
Signed-off-by: York Sun
29 Mar, 2017
1 commit
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MAC number used per QSGMII is not fixed. It may wary from SoC to SoC.
So move QSGMII wriop_init_dpmac() to SoC file.
Signed-off-by: Prabhakar Kushwaha
Signed-off-by: Ashish Kumar
Reviewed-by: York Sun
22 Nov, 2016
1 commit
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Signed-off-by: Priyanka Jain
Signed-off-by: Prabhakar Kushwaha
Signed-off-by: Ashish Kumar
Acked-by: Joe Hershberger
Reviewed-by: York Sun
04 May, 2016
1 commit
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Memset pools_params as "0" to avoid garbage value in dpni_set_pools.
Signed-off-by: Prabhakar Kushwaha
Reported-by: Jose Rivera
Acked-by: Joe Hershberger
07 Apr, 2016
1 commit
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LS2080A is the primary SoC, and LS2085A is a personality with AIOP
and DPAA DDR. The RDB and QDS boards support both personality. By
detecting the SVR at runtime, a single image per board can support
both SoCs. It gives users flexibility to swtich SoC without the need
to reprogram the board.Signed-off-by: York Sun
CC: Prabhakar Kushwaha
Reviewed-by: Prabhakar Kushwaha
22 Mar, 2016
1 commit
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This patch integrate DPAA2 ethernet driver existing PHY framework.
Call phy_connect and phy_config as per available DPMAC id defined
in SerDes Protcol.Signed-off-by: Pratiyush Mohan Srivastava
Signed-off-by: Prabhakar Kushwaha
Reviewed-by: York Sun
28 Jan, 2016
5 commits
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Add debug information prints to provide DPMAC statistics
- Number of bytes received
- Number of received and discard frames
- Number of bytes transferred
- Number of frames transferred
etc.Signed-off-by: Prabhakar Kushwaha
Reviewed-by: York Sun -
Management Complex FW 9.0 set the hardware depletion to be 20
buffers in order to support multiple pools in DPNI. This requires
driver to fill the pool with at least 21 to be able to receive
frames. So, Increase number of buffers for a pool.Signed-off-by: Prabhakar Kushwaha
Reviewed-by: York Sun -
Management Complex FW 9.0 puts a new requirement to provide Tx
confirmation and error queue configuration by calling
dpni_set_tx_conf API.Configure report of only error frames for a tx frame.
Signed-off-by: Prabhakar Kushwaha
Reviewed-by: York Sun -
MC firmware version 9.0.0 contains
- Support of new APIs
- Update in existing APIs
- Change in Major and minor version of DPAA2 objectsThis patch contains modifications in FLIB files to support new
MC firmware version.Signed-off-by: Prabhakar Kushwaha
Reviewed-by: York Sun -
Check and compare version of management complex's object with
the version supported by Freescale ldpaa2 ethernet driver.Signed-off-by: Prabhakar Kushwaha
Reviewed-by: York Sun
15 Jan, 2016
1 commit
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With format-security errors turned on, GCC picks up the use of sprintf with
a format parameter not being a string literal.Simple uses of sprintf are also converted to use strcpy.
Signed-off-by: Ben Whitten
Acked-by: Wolfgang Denk
Reviewed-by: Tom Rini
01 Dec, 2015
4 commits
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Freescale's LS2085A is a another personality of LS2080A SoC with
support of AIOP and DP-DDR.
This Patch adds support of LS2085A Personality.Signed-off-by: Pratiyush Mohan Srivastava
Signed-off-by: Prabhakar Kushwaha
[York Sun: Updated MAINTAINERS files
Dropped #ifdef in cpu.h
Add CONFIG_SYS_NS16550=y in defconfig]
Reviewed-by: York Sun -
LS2080A is a prime personality of Freescale’s LS2085A. It is a non-AIOP
personality without support of DP-DDR, L2 switch, 1588, PCIe endpoint etc.
So renaming existing LS2085A code base to reflect LS2080A (Prime personality)Signed-off-by: Pratiyush Mohan Srivastava
Signed-off-by: Prabhakar Kushwaha
[York Sun: Dropped #ifdef in cpu.c for cpu_type_list]
Reviewed-by: York Sun -
MC 0.7.1.2 enforces limitation i.e.: "Packets may be corrupted
in several combinations of buffer size and frame offsets.
Workaround: Use buffers that are of size that is a multiple of 256, and
frame offset that is a multiple of 256"Updating the DPNI Eth driver to comply with the restriction.
Signed-off-by: Bogdan Hamciuc
Signed-off-by: Prabhakar Kushwaha
Reviewed-by: York Sun -
Add following debug information in the driver
- Get various DPNI counter values
- Get link status of DPNI objects
- Get information of both ends of connection (DPMAC - DPNI)Signed-off-by: Prabhakar Kushwaha
Reviewed-by: York Sun