06 May, 2020

1 commit


06 Feb, 2020

2 commits

  • At present dm/device.h includes the linux-compatible features. This
    requires including linux/compat.h which in turn includes a lot of headers.
    One of these is malloc.h which we thus end up including in every file in
    U-Boot. Apart from the inefficiency of this, it is problematic for sandbox
    which needs to use the system malloc() in some files.

    Move the compatibility features into a separate header file.

    Signed-off-by: Simon Glass

    Simon Glass
     
  • At present devres.h is included in all files that include dm.h but few
    make use of it. Also this pulls in linux/compat which adds several more
    headers. Drop the automatic inclusion and require files to include devres
    themselves. This provides a good indication of which files use devres.

    Signed-off-by: Simon Glass
    Reviewed-by: Anatolij Gustschin

    Simon Glass
     

27 Jan, 2020

1 commit


25 Jan, 2020

1 commit

  • Since every Allwinner USB PHY seems to be slightly different from each
    other, we need to add the compatible string and the respective data
    structure to make it work on the R40/V40 SoC.
    Nothing spectacular this time, just one less USB controller than the H3.
    Copied from the Linux kernel.

    Signed-off-by: Andre Przywara
    Reviewed-by: Jagan Teki

    Andre Przywara
     

20 Jan, 2020

2 commits

  • AM654 SoC has USB2 PHY which is similar to existing USB2 PHYs on OMAP
    SoCs. Add support for the same.

    Signed-off-by: Vignesh Raghavendra
    Reviewed-by: Marek Vasut
    Signed-off-by: Lokesh Vutla

    Vignesh Raghavendra
     
  • Below warning is seen when this driver is built for devices with 64 bit
    physical address space.

    drivers/phy/omap-usb2-phy.c: In function ‘omap_usb2_phy_probe’:
    drivers/phy/omap-usb2-phy.c:187:20: warning: cast to pointer from integer of different size [-Wint-to-pointer-cast]
    priv->phy_base = (void *)base;
    ^
    Fix this by using dev_read_addr_ptr() instead of dev_read_addr().

    Signed-off-by: Vignesh Raghavendra
    Reviewed-by: Marek Vasut
    Signed-off-by: Lokesh Vutla

    Vignesh Raghavendra
     

16 Jan, 2020

2 commits


26 Dec, 2019

4 commits


31 Oct, 2019

1 commit


26 Oct, 2019

1 commit


25 Oct, 2019

1 commit


24 Oct, 2019

1 commit


11 Oct, 2019

1 commit

  • The driver provides PHY for USB2, USB3.0, PCIe and SATA, and now
    we just enable PCIe. As for the other functionalities will be
    added gradually in upcoming days.

    This is adapted from the Linux version.

    Tested-by: Frank Wunderlich
    Signed-off-by: Ryder Lee
    Signed-off-by: Frank Wunderlich

    Ryder Lee
     

26 Aug, 2019

1 commit

  • Several options are presenting themselves on a various boards
    where the options are clearly not used. (ie, SPL/TPL options
    when SPL or TPL are not defined)

    This patch is not attempting to be a complete list of items, but
    more like low hanging fruit. In some instances, I wasn't sure
    of DM was required, so I simply made them SPL or TPL.

    This patch attempts to reduce some of the menuconfig noise
    by defining dependencies so they don't appear when not used.

    Signed-off-by: Adam Ford

    Adam Ford
     

13 Aug, 2019

1 commit

  • Add a new SERDES driver for TI's AM654x SoC which configures
    the SERDES only for PCIe. Support fo USB3 can be added later.

    SERDES in am654x has three input clocks (left input, external
    reference clock and right input) and two output clocks (left
    output and right output) in addition to a PLL mux clock which
    the SERDES uses for Clock Multiplier Unit (CMU refclock).

    The PLL mux clock can select from one of the three input
    clocks. The right output can select between left input and
    external reference clock while the left output can select
    between the right input and external reference clock.

    The driver has support to select PLL mux and left/right output
    mux as specified in device tree.

    Signed-off-by: Sekhar Nori

    Sekhar Nori
     

08 Aug, 2019

1 commit


16 Jul, 2019

1 commit

  • The USB PHY used in the Allwinner H6 SoC has some pecularities (as usual),
    which require a small addition to the USB PHY driver:
    In this case the second PHY is PHY3, not PHY1, so we need to skip number
    1 and 2 in the code. Just use the respective code from Linux for that.

    Signed-off-by: Andre Przywara
    Tested-by: Corentin Labbe # Pine-H64
    Reviewed-by: Jagan Teki

    Andre Przywara
     

09 May, 2019

1 commit

  • This adds support for the USB PHYs found in the Amlogic G12A SoC Family.

    The USB2 PHY supports Host and/or Peripheral mode, depending on it's position.
    The first PHY is only used as Host, but the second supports Dual modes
    defined by the USB Control Glue HW in front of the USB Controllers.

    The second driver supports USB3 Host mode or PCIE 2.0 mode, depending on
    the layout of the board.
    Selection is done by the #phy-cells, making the mode static and exclusive.

    Signed-off-by: Neil Armstrong

    Neil Armstrong
     

21 Apr, 2019

5 commits


12 Apr, 2019

1 commit

  • This driver is derived from this Linux driver:
    linux/drivers/phy/ralink/phy-ralink-usb.c

    The driver sets up power and host mode, but also needs to configure PHY
    registers for the MT7628 and MT7688.

    I removed the reset controller handling for the USB host and device, as
    it does not seem to be necessary right now. The soft reset bits for both
    devices are enabled by default and testing has shown (with hackish
    reset handling added), that USB related commands work identical with
    or without the reset handling.

    Please note that the resulting USB support is tested only very minimal.
    I was able to detect one of my 3 currently available USB sticks.
    Perhaps some further work is needed to fully support the EHCI controller
    integrated in the MT76x8 SoC.

    Signed-off-by: Stefan Roese
    Cc: Marek Vasut
    Cc: Daniel Schwierzeck
    Reviewed-by: Daniel Schwierzeck

    Stefan Roese
     

03 Apr, 2019

1 commit


19 Jan, 2019

1 commit


15 Dec, 2018

2 commits


07 Dec, 2018

2 commits


28 Oct, 2018

1 commit


03 Oct, 2018

1 commit


01 Oct, 2018

1 commit


19 Sep, 2018

2 commits

  • This patch adds support to Armada 7k/8k comphy RX/TX lane swap. The
    'phy-invert' DT property defines the inverted signals.

    Signed-off-by: Rabeeh Khoury
    Signed-off-by: Baruch Siach
    Signed-off-by: Stefan Roese

    Rabeeh Khoury
     
  • This adds a weak definition of comphy_update_map to comphy_core,
    which does nothing. If this function is defined elsewhere, for example
    in board file, the board file can change some parameters of SERDES
    configuration.

    This is needed on Turris Mox, where the SERDES speed on lane 1 has to
    be set differently when SFP module is connected and when Topaz Switch
    module is connected.

    This is a temporary solution. When the comphy driver for armada-3720
    will be added to the kernel, the comphy driver in u-boot shall also be
    updated and this should be done differently then.

    Signed-off-by: Marek Behun
    Signed-off-by: Stefan Roese

    Marek Behún