Eric Lee / smarc-uboot

20 Nov, 2020

1 commit

19 Oct, 2020

2 commits

  • dc1d49ef1   MLK-24876: spi:fsl_fspi: fix build warnning ... Browse Code »

    fix the fspi read function build warning

    The fspi IPS read function was not used since all configs enabled the
    AHB read. Fixed the warning after disable AHB read on iMX8DXL.

    Signed-off-by: Han Xu
    (cherry picked from commit 5be6af1ccd237f785325f8ffdfa65cd6e2ad7904)

    Han Xu
     
  • 44253969c   MLK-24766-1 spi: fsl_lpspi: add lpspi driver for uboot ... Browse Code »
    1

    Add the LPSPI driver for imx7ulp/8qxp/8dxl/8qm.
    Need to enable these two options to use this driver:
    CONFIG_DM_SPI=y
    CONFIG_FSL_LPSPI=y

    Signed-off-by: Clark Wang
    Reviewed-by: Ye Li
    Reviewed-by: Fugang Duan
    (cherry picked from commit 01a03144cf1f1cbefd4a829a1980759e1bf57b6a)

    Clark Wang
     

28 Aug, 2020

1 commit

26 Aug, 2020

1 commit

25 Aug, 2020

15 commits

03 Jun, 2020

2 commits

  • 6cbc8b589   fsl_qspi: Provide config to map full AHB space ... Browse Code »

    iMX platforms provide large AHB mapped space for QSPI, each
    controller has 256MB. However, current driver only maps small
    size (AHB buffer size) of AHB space, this implementation
    causes iMX failed to boot M4 with QSPI XIP image.

    Add config CONFIG_FSL_QSPI_AHB_FULL_MAP (default enabled for iMX)
    to address above problem.

    When the config is set:
    1. Full AHB space is divided to each CS.
    2. A dedicated LUT entry is used for AHB read only.
    3. The MODE instruction in LUT is replaced to standard ADDR instruction
    4. The address in spi_mem_op is used to SFAR and AHB read

    Signed-off-by: Ye Li

    Ye Li
     
  • 990b4fff6   fsl_qspi: add support for iMX7ULP ... Browse Code »

    Add compatible string and driver data for iMX7ULP.
    The address in SFA1AD/SFA2AD/SFB1AD/SFB2AD must align with 1KB.
    For iMX7ULP which has only 128Bytes AHB buffer, must align it when
    setting the registers.

    Signed-off-by: Ye Li

    Ye Li
     

08 May, 2020

1 commit

  • 15fcf111e   Merge remote-tracking branch 'remotes/origin/dn_uboot' into imx_uboot ... Browse Code »

    Conflicts:
    drivers/spi/fsl_qspi.c
    include/configs/mx6sxsabresd.h
    include/configs/mx6ul_14x14_evk.h
    include/configs/mx6ullevk.h

    According to the feedback from Priyanka and Ashish, the qspi framework has
    big changes to port the existing Linux driver to replace the old qspi driver.
    The patches has been accepted in the u-boot upstream and will be in 2020.07

    So, the suggestion is to override the imx_uboot conflicts, which means some
    platform support is droppped such as the imx7ulp(not on the Linux upstream)
    and some imx local patches need be reworked based on community new qspi driver

    This need Li Ye and Han Xu to rework on the imx port

    Signed-off-by: Jason Liu

    Jason Liu
     

06 May, 2020

4 commits

  • a56bf035b   MLK-22556-1 spi: flexspi_nand: Add new flexspi nand driver ... Browse Code »
    1

    Add flexspi_nand driver which works on iMX flexspi controller to support
    SPI NAND flash. This driver requires DM_SPI and follows SPI-MEM interfaces
    to adapt to the SPI NAND framework.

    Note: Current implementation limits to the 12-bit column address. This is
    popular in main stream SPI NAND and flash devices supported in u-boot.
    If device with larger page size (> 4096) needs to support, we have to change
    the driver.

    Signed-off-by: Ye Li
    (cherry picked from commit d5c2580a245fa0cd4ae0012ceb5c8bd2f497f19c)

    Ye Li
     
  • 0633c42f9   MLK-12483-4 mx6: Modify drivers to disable fused modules ... Browse Code »
    1

    Add the fuse checking in drivers, when the module is disabled in fuse,
    the driver will not work.

    Changed drivers: BEE, GPMI, APBH-DMA, ESDHC, FEC, QSPI, ECSPI, I2C,
    USB-EHCI, GIS, LCDIF and EPDC.

    Signed-off-by: Ye Li
    (cherry picked from commit 1704e116f9b39aeb99201919a18bc2b1e19a980e)
    (cherry picked from commit 2d3b5df8530cd5ef883750378838dea7c40259af)
    (cherry picked from commit 6e8c9ae136bee8ec0121c1db4b935510caad09db)
    (cherry picked from commit 99b54a6965904a879afdb6883a519de726cb4e96)

    Ye Li
     
  • 2e881a422   MLK-17656: mtd: qspi: support read the flag status in fspi driver ... Browse Code »

    support to read the flag status in driver to avoid the spi-nor framework
    wait_for_ready hang issue.

    Signed-off-by: Han Xu
    (cherry picked from commit 767faa948d2d140b6d56ee505f81f8f57c045a3d)
    (cherry picked from commit 55e83ccb588c3e953f55148161bc524b5dab7a25)
    (cherry picked from commit 92b281f91792ffc76e9541fa341d6f46c6ec2b7a)

    Han Xu
     
  • 5173e1dfb   MLK-23574-2 spi: Add FlexSPI Driver for i.MX8 ... Browse Code »

    Port fsl_fspi driver for flexspi controller from imx_v2019.04.
    This driver supports:
    1. DDR Quad output
    2. Prefetch function for improve read performance.
    3. Fast read and Quad read for one line read mode.
    4. Read flash FSR register.
    5. DM driver and SPI-MEM supported

    Signed-off-by: Han Xu
    Signed-off-by: Ye Li
    (cherry picked from commit ae4e80b7b0debd2ad868781aaeb28ca4f2d9a8aa)
    (cherry picked from commit dcd5504f6493d9aed415f397f1c13611fc202605)
    (cherry picked from commit 902fba8f72e98d6c742674d305c855f3595c48b6)

    Ye Li
     

01 May, 2020

1 commit

  • 8e904df60   spi: Transform the FSL QuadSPI driver to use the SPI MEM API ... Browse Code »

    To support the SPI MEM API, instead of modifying the existing U-Boot
    driver, this patch adds a port of the existing Linux driver.
    This also has the advantage that porting changes and fixes from Linux will
    be easier.
    Porting of driver left most of the functions unchanged while few of the
    changes are:
    -Remove lock(mutexes) and irq handler as u-boot is a single core execution.
    -Remove invalid masterid as it was required specially for multicore
    execution in LS2088ARDB which is not the case in u-boot.
    -Remove clock support as changing spi speed is not supported in uboot and
    nor in linux.

    Currently tested on LS1088ARDB, LS1012ARDB, LS1046ARDB, LS1046AFRWY,
    LS1043AQDS, LS1021ATWR, LS2088ARDB, I.MX6ULL EVK.

    Signed-off-by: Frieder Schrempf
    Signed-off-by: Ashish Kumar
    Signed-off-by: Kuldeep Singh
    Reviewed-by: Stefan Roese
    Tested-by: Stefan Roese
    Acked-by: Vignesh Raghavendra

    Kuldeep Singh
     

27 Apr, 2020

1 commit

  • ffb365800   spi: nxp-fspi: Add 1us delay to make controller ready for next transaction ... Browse Code »

    Board gets reset when performing burst read/write operations. On the
    other hand, no such behaviour is observed on small size operations.

    In Linux, readl_poll_timeout API already add delay of 1us which is
    skipped in U-boot. Since, NXP Flexspi U-boot driver is a ported version
    of Linux driver and U-boot poll_timeout API lacks delay functionality,
    add 1us delay so as to make controller ready for other transactions.

    Signed-off-by: Kuldeep Singh

    Kuldeep Singh
     

04 Apr, 2020

1 commit

03 Apr, 2020

3 commits

  • b1747fdb8   qspi: t210: Use dev_read calls to get FDT data like base, freq ... Browse Code »

    This Tegra QSPI driver hadn't been brought up to date with how
    DM drivers are fetching data from the FDT now, and was pulling
    in bogus data for base, max freq, etc. Fixed ofdata_to_platdata
    to work the same way it does in the tegra114 SPI driver, using
    dev_read_ functions.

    Signed-off-by: Tom Warren

    Tom Warren
     
  • 2fcc3ba1b   qspi: t210: Fix QSPI clock and tap delays ... Browse Code »

    When claim_bus was setting the clock, it reset the QSPI controller,
    which wipes out any tap delays set by previous bootloaders (nvtboot,
    CBoot for example on Nano). Instead of doing that in claim_bus, which
    gets called a lot, moved clock setting to probe(), and set tap delays
    there, too. Also updated clock to 80MHz to match CBoot. Now QSPI env
    save works reliably again.

    Signed-off-by: Tom Warren

    Tom Warren
     
  • 3c8cf2403   qspi: t210: Fix claim_bus's use of the wrong bus/device ... Browse Code »

    claim_bus() is passed a udevice *dev, which is the bus device's parent.
    In this driver, claim_bus assumed it was the bus, which caused the
    'priv' info pointer to be wrong, and periph_id was incorrect. This in
    turn caused the periph clock call to assign the wrong clock (PLLM
    instead of PLLP0), which caused a kernel warning. I only saw the 'bad'
    periph_id when enabling DEBUG due to an assert. Not sure how QSPI was
    working w/this errant clock, but it was moot as QSPI wasn't active
    unless you probed it, and that wasn't happening until I posted a patch
    to enable env save to QSPI for Nano (coming soon).

    Signed-off-by: Tom Warren

    Tom Warren
     

02 Apr, 2020

2 commits

  • 52e2565bf   spi: atmel-quadspi: Add verbose debug facilities to monitor register accesses ... Browse Code »
    1

    This feature should not be enabled in release but can be useful for
    developers who need to monitor register accesses at some specific places.

    Helped me identify a bug in u-boot, by comparing the register accesses
    from the u-boot driver with the ones from its linux variant.

    Signed-off-by: Tudor Ambarus
    [jagan: use 16 bit array with tmp variable]
    Signed-off-by: Jagan Teki
    Reviewed-by: Jagan Teki

    Tudor Ambarus
     
  • ba03a6c94   spi: atmel-quadspi: fix possible MMIO window size overrun ... Browse Code »

    The sama5d2 QSPI controller memory space is limited to 128MB:
    0x9000_00000-0x9800_00000/0XD000_0000--0XD800_0000.

    There are nor flashes that are bigger in size than the memory size
    supported by the controller: Micron MT25QL02G (256 MB).

    Check if the address exceeds the MMIO window size. An improvement
    would be to add support for regular SPI mode and fall back to it
    when the flash memories overrun the controller's memory space.

    Fixes: 24c8ff4684c5 ("spi: Add Atmel QuadSPI driver")
    Signed-off-by: Tudor Ambarus
    Reviewed-by: Jagan Teki

    Tudor Ambarus
     

31 Mar, 2020

3 commits

  • 4856cc7a9   mpc8xxx_spi: implement real ->set_speed ... Browse Code »
    1

    Not all boards have the same CSB frequency, nor do every SPI slave
    necessarily support running at 16.7 MHz. So implement ->set_speed;
    that also allows using a smaller PM (i.e., 0) for slaves that do
    support a higher speed.

    Based on work by Klaus H. Sørensen.

    Cc: Klaus H. Sorensen
    Signed-off-by: Rasmus Villemoes

    Rasmus Villemoes
     
  • 391c40048   mpc8xxx_spi: always use 8-bit characters, don't read or write garbage ... Browse Code »

    There are a few problems with the current driver.

    First, it unconditionally reads from dout/writes to din whether or not
    those pointers are NULL. So for example a simple "sf probe" ends up
    writing four bytes at address 0:

    => md.l 0x0 8
    00000000: 45454545 45454545 05050505 05050505 EEEEEEEE........
    00000010: 00000000 00000000 07070707 07070707 ................
    => sf probe 0
    mpc8xxx_spi_xfer: slave spi@7000:0 dout 0FB53618 din 00000000 bitlen 8
    mpc8xxx_spi_xfer: slave spi@7000:0 dout 00000000 din 0FB536B8 bitlen 48
    SF: Detected s25sl032p with page size 256 Bytes, erase size 64 KiB, total 4 MiB
    => md.l 0x0 8
    00000000: ff000000 45454545 05050505 05050505 ....EEEE........
    00000010: 00000000 00000000 07070707 07070707 ................

    (here I've change the first debug statement to a printf, and made it
    print the din/dout pointers rather than the uints they point at).

    Second, as we can also see above, it always writes a full 32 bits,
    even if a smaller amount was requested. So for example

    => mw.l $loadaddr 0xaabbccdd 8
    => md.l $loadaddr 8
    02000000: aabbccdd aabbccdd aabbccdd aabbccdd ................
    02000010: aabbccdd aabbccdd aabbccdd aabbccdd ................
    => sf read $loadaddr 0x400 6
    device 0 offset 0x400, size 0x6
    mpc8xxx_spi_xfer: slave spi@7000:0 dout 0FB536E8 din 00000000 bitlen 40
    mpc8xxx_spi_xfer: slave spi@7000:0 dout 00000000 din 02000000 bitlen 48
    SF: 6 bytes @ 0x400 Read: OK
    => sf read 0x02000010 0x400 8
    device 0 offset 0x400, size 0x8
    mpc8xxx_spi_xfer: slave spi@7000:0 dout 0FB53848 din 00000000 bitlen 40
    mpc8xxx_spi_xfer: slave spi@7000:0 dout 00000000 din 02000010 bitlen 64
    SF: 8 bytes @ 0x400 Read: OK
    => md.l $loadaddr 8
    02000000: 45454545 45450000 aabbccdd aabbccdd EEEEEE..........
    02000010: 45454545 45454545 aabbccdd aabbccdd EEEEEEEE........

    Finally, when the bitlen is 24 mod 32 (e.g. requesting to read 3 or 7
    bytes), the last three bytes and up being the wrong ones, since the
    driver does a full 32 bit read and then shifts the wrong byte out:

    => mw.l $loadaddr 0xaabbccdd 4
    => md.l $loadaddr 4
    02000000: aabbccdd aabbccdd aabbccdd aabbccdd ................
    => sf read $loadaddr 0x444 10
    device 0 offset 0x444, size 0x10
    mpc8xxx_spi_xfer: slave spi@7000:0 dout 0FB536E8 din 00000000 bitlen 40
    mpc8xxx_spi_xfer: slave spi@7000:0 dout 00000000 din 02000000 bitlen 128
    SF: 16 bytes @ 0x444 Read: OK
    => md.l $loadaddr 4
    02000000: 552d426f 6f742032 3031392e 30342d30 U-Boot 2019.04-0
    => mw.l $loadaddr 0xaabbccdd 4
    => sf read $loadaddr 0x444 0xb
    device 0 offset 0x444, size 0xb
    mpc8xxx_spi_xfer: slave spi@7000:0 dout 0FB536E8 din 00000000 bitlen 40
    mpc8xxx_spi_xfer: slave spi@7000:0 dout 00000000 din 02000000 bitlen 88
    SF: 11 bytes @ 0x444 Read: OK
    => md.l $loadaddr 4
    02000000: 552d426f 6f742032 31392e00 aabbccdd U-Boot 219......

    Fix all of that by always using a character size of 8, and reject
    transfers that are not a whole number of bytes. While it ends being
    more work for the CPU, we're mostly bounded by the speed of the SPI
    bus, and we avoid writing to the mode register in every loop.

    Based on work by Klaus H. Sørensen.

    Cc: Klaus H. Sorensen
    Signed-off-by: Rasmus Villemoes

    Rasmus Villemoes
     
  • 1a7b462de   mpc8xxx_spi: put max_cs to use ... Browse Code »
    1

    Currently, max_cs is write-only; it's just set in
    mpc8xxx_spi_ofdata_to_platdata and not otherwise used.

    My mpc8309 was always resetting during an "sf probe 0". It turns out
    dm_gpio_set_dir_flags() was being called with garbage, since nothing
    had initialized priv->gpios[0] - our device tree used "cs-gpios"
    rather than "gpios", so gpio_request_list_by_name() had returned 0.

    That would have been a lot easier to figure out if the chip select
    index was sanity checked, so rename max_cs to cs_count, and reject a
    xfer with a too large cs index.

    Signed-off-by: Rasmus Villemoes

    Rasmus Villemoes
     

06 Feb, 2020

2 commits