05 May, 2013
2 commits
-
Legacy iomux support is no longer needed now that all boards have been converted
to iomux-v3.Signed-off-by: Benoît Thébaudeau
Reviewed-by: Marek Vasut -
Add support for generic NAND SPL via the SPL framework into the
mxc_nand_spl driver. This is basically just a simple rename and
publication of the already implemented functions. To avoid the
bare-bones functions getting in the way of the NAND_SPL, build
them only if CONFIG_SPL_FRAMEWORK is not defined.Also make sure the requested payload is aligned to full pages,
otherwise this simple driver fails to load the last page.Signed-off-by: Marek Vasut
Cc: Albert ARIBAUD
Cc: Benoît Thébaudeau
Cc: Fabio Estevam
Cc: Scott Wood
Cc: Stefano Babic
Cc: Tom Rini
Acked-by: Scott Wood
28 Apr, 2013
2 commits
-
Add an mxc_ocotp driver for i.MX6.
Signed-off-by: Benoît Thébaudeau
-
Add a fsl_iim driver common to i.MX and MPC.
Signed-off-by: Benoît Thébaudeau
22 Apr, 2013
3 commits
-
Signed-off-by: Stefan Roese
Acked-by: Scott Wood
Cc: Stefano Babic
Cc: Marek Vasut
Cc: Fabio Estevam -
This will be used by the i.MX6 NAND support.
Signed-off-by: Stefan Roese
Cc: Stefano Babic
Cc: Marek Vasut
Cc: Fabio Estevam -
The following headers are moved to a i.MX common location:
- regs-common.h
- regs-apbh.h
- regs-bch.h
- regs-gpmi.h
- dma.hThis way this header can be re-used also by other i.MX platforms.
For example the i.MX6 which will need it for the upcoming NAND
support.Signed-off-by: Stefan Roese
Cc: Stefano Babic
Cc: Marek Vasut
Cc: Fabio Estevam
14 Apr, 2013
4 commits
-
Rework the waiting for transfer completion loop condition
to continue waiting until both Transfer Complete and DMA End
interrupts occur. Checking of DLA bit in Present State register
looks not needed in addition to interrupts status checking,
so it can be removed from the condition. Also, DMA Error
condition is added to the list of data errors, checked in the loop.Signed-off-by: Andrew Gabbasov
-
The cache should invalidate the read buffer for
the SD card interface after the transfer complete,
not command-complete.Tested-by: Andrew Gabbasov
Signed-off-by: Eric Nelson
13 Apr, 2013
3 commits
-
The glitch in the SPI clock line, which commit 3cea335c34 (spi: mxc_spi: Fix spi
clock glitch durant reset) solved, is back now and itwas re-introduced by
commit d36b39bf0d (spi: mxc_spi: Fix ECSPI reset handling).Actually the glitch is happening due to always toggling between slave mode
and master mode by configuring the CHANNEL_MODE bits in this reset function.Since the spi driver only supports master mode, set the mode for all channels
always to master mode in order to have a stable, "glitch-free" SPI clock line.Signed-off-by: Fabio Estevam
-
Conflicts:
drivers/video/exynos_fb.c -
If CONFIG_NAND_ECC_BCH is set use 4-bit error correction code instead of
the 1-bit error correction code on the NAND device.Signed-off-by: Gerlando Falauto
Signed-off-by: Holger Brunck
cc: Valentin Longchamp
cc: Prafulla Wadaskar
Acked-by: Prafulla Wadaskar
Acked-by: Scott Wood
12 Apr, 2013
10 commits
-
Following the removal of the smdk6400 board, the s3c64xx SoC becomes unused, so
remove associated code. It will still be possible to restore it later from the
Git history if necessary.Signed-off-by: Benoît Thébaudeau
-
This also fixes support for mx31pdk and tx25, which had been broken by commit
e05e5de7fae5bec79617e113916dac6631251156.Signed-off-by: Benoît Thébaudeau
Acked-by: Scott Wood
Tested-by: Fabio Estevam -
The syndrome functions should use the page number passed as argument instead of
the page number saved upon NAND_CMD_READ0.This does not make any difference if the NAND_NO_AUTOINCR option is set, but
otherwise this fixes accesses to the wrong pages.Signed-off-by: Benoît Thébaudeau
Acked-by: Scott Wood -
The page number indicated in the debug trace of mxc_nand_read_oob_syndrome() did
not match the page being worked on.By the way, replace the GCC-specific __FUNCTION__ with __func__.
Signed-off-by: Benoît Thébaudeau
Acked-by: Scott Wood -
Signed-off-by: Benoît Thébaudeau
Acked-by: Scott Wood
Tested-by: Fabio Estevam -
Add some abstraction to NFC definitions so that some parts of the current code
can also be used for future i.MX5 code.Clean up a few things by the way.
Signed-off-by: Benoît Thébaudeau
Acked-by: Scott Wood
Tested-by: Fabio Estevam -
Currently is_16bit_nand() is a per SoC function and it decides the bus nand
width by reading some boot related registers.This method works when NAND is the boot medium, but does not work if another
boot medium is used. For example: booting from a SD card and then using NAND
to store the environment variables, would lead to the following error:NAND bus width 16 instead 8 bit
No NAND device found!!!
0 MiBUse CONFIG_SYS_NAND_BUSWIDTH_16BIT symbol to decide the bus width.
If it is defined in the board file, then consider 16-bit NAND bus-width,
otherwise assume 8-bit NAND is used.This also aligns with Documentation/devicetree/bindings/mtd/nand.txt, which
states:nand-bus-width : 8 or 16 bus width if not present 8
Signed-off-by: Fabio Estevam
Acked-by: Scott Wood
Reviewed-by: Benoît Thébaudeau -
Introduce CONFIG_SYS_NAND_BUSWIDTH_16BIT option so that other NAND controller
drivers could use it when a 16-bit NAND is deployed.drivers/mtd/nand/ndfc has CONFIG_SYS_NDFC_16BIT, so just rename it, so that
other NAND drivers could reuse the same symbol.Signed-off-by: Fabio Estevam
Acked-by: Scott Wood
Reviewed-by: Benoît Thébaudeau -
The prints are out of control. SILENCE!
Signed-off-by: Joe Hershberger
-
The unwind code was not reversing operations correctly and was causing
a hang on any error condition.Signed-off-by: Joe Hershberger
10 Apr, 2013
3 commits
-
Support for NAND storage devices to work with the DFU framework.
Signed-off-by: Pantelis Antoniou
Signed-off-by: Tom Rini
Acked-by: Scott Wood -
We make these two functions take a size_t pointer to how much space
was used on NAND to read or write the buffer (when reads/writes happen)
so that bad blocks can be accounted for. We also make them take an
loff_t limit on how much data can be read or written. This means that
we can now catch the case of when writing to a partition would exceed
the partition size due to bad blocks. To do this we also need to make
check_skip_len count not just complete blocks used but partial ones as
well. All callers of nand_(read|write)_skip_bad are adjusted to call
these with the most sensible limits available.The changes were started by Pantelis and finished by Tom.
Signed-off-by: Pantelis Antoniou
Signed-off-by: Tom Rini -
Previously we didn't support upload/download larger than available
memory. This is pretty bad when you have to update your root filesystem
for example.This patch removes that limitation (and the crashes when you transfered
any file larger than 4MB) by making raw image writes be done in chunks
and making file maximum size be configurable.The sequence number is a 16 bit counter; make sure we handle rollover
correctly. This fixes the wrong transfers for large (> 256MB) images.Also utilize a variable to handle initialization, so that we don't rely
on just the counter sent by the host.Signed-off-by: Pantelis Antoniou
Signed-off-by: Tom Rini
09 Apr, 2013
1 commit
-
Following commit:
"cmd_ext4: BREAK and correct ext4write parameter order"
SHA1:0171d52c410cbaa9290b1b214e695697c835bfe5introduced cleanup of ext4write semantics to be consistent with other
filesystem's writing commands (e.g. fatwrite).
This commit provides correct ext4write command generation at DFU eMMC
code.Signed-off-by: Lukasz Majewski
Signed-off-by: Kyungmin Park
08 Apr, 2013
6 commits
-
The kernel states:
---88---
And we do so in u-boot.
This implementation uses the same layout for BCH8 but it is fix. The current
provided layout does only work with 64 Byte OOB.Signed-off-by: Andreas Bießmann
Cc: Tom Rini
Cc: Ilya Yanok
Cc: Scott Wood
Cc: Mansoor Ahamed
Cc: Thomas Weber -
With uppcoming BCH support on OMAP devices we need to decide between differnt
algorithms when switching the ECC engine. Currently we support 1-bit hammign
and 8-bit BCH on HW backend.In order to switch between differnet ECC algorithms we need to change the
interface of omap_nand_switch_ecc() also.Signed-off-by: Andreas Bießmann
Cc: Tom Rini
Cc: Thomas Weber -
arch/arm/include/asm/arch-am33xx/omap_gpmc.h and
arch/arm/include/asm/arch-omap3/omap_gpmc.h are almost the same, consolidate
the common parts into a new header.Introduce a new asm/omap_gpmc.h which defines the command part and pulls in
the architecture specific one.Signed-off-by: Andreas Bießmann
Cc: Tom Rini
Reviewed-by: Tom Rini -
Flush UART3 xmit on enable if TEMT is broken
On some OMAP3 devices when UART3 is configured for boot mode before SPL starts
only THRE bit is set. We have to empty the transmitter before initialization
starts. This patch avoids the use of CONFIG_SYS_NS16550_BROKEN_TEMT.Signed-off-by: Manfred Huber
Tested-by: Javier Martinez Canillas
Tested-by: Andreas Bießmann -
Do not config MUSB to highspeed mode if CONFIG_USB_GADGET_DUALSPEED
is not set, in which case Ether gadget only operates in fullspeed.Reviewed-by: Tom Rini
Signed-off-by: Bin Liu -
On TI AM335x devices, MUSB has bulk split/combine feature enabled
in the ConfigData register, but the current MUSB driver does not
support it yet. Therefore, disable the feature for now, until the
driver adds the support.One usecase which is broken because of this feature is that Ether
gadget stops working in Fullspeed mode (by un-defining
CONFIG_USB_GADGET_DUALSPEED)After desabled this feature, MUSB driver send packets in proper size
(no more than 64 bytes) in Fullspeed mode.This has been validated with Ether gadget in Fullspeed mode on AM335x
EVM.Signed-off-by: Bin Liu
05 Apr, 2013
1 commit
04 Apr, 2013
5 commits
-
Reviewing the ECSPI reset handling shows two issues:
1. For the enable/reset bit (MXC_CSPICTRL_EN) in the control reg
(ECSPIx_CONGREG) the i.MX6 technical reference manual states:-- cut --
ECSPIx_CONREG[0]: EN: Writing zero to this bit disables the block
and resets the internal logic with the exception of the ECSPI_CONREG.
-- cut --Note the exception mentioned: The CONREG itself isn't reset.
Fix this by manually writing the reset value 0 to the whole register.
This sets the EN bit to zero, too (i.e. includes the old
~MXC_CSPICTRL_EN).2. We want to reset the whole SPI block here. So it makes no sense
to first read the old value of the CONREG and write it back, later.
This will give us the old (historic/random) value of the CONREG back.
And doesn't reset the CONREG.To get a clean CONREG after the reset of the block, too, don't use
the old (historic/random) value of the CONREG while doing the reset.
And read the clean CONREG after the reset.This was found while working on a SPI boot device where the i.MX6 boot
ROM has already initialized the SPI block. The initialization by the
boot ROM might be different to what the U-Boot driver wants to configure.
I.e. we need a clean reset of SPI block, including the CONREG.Signed-off-by: Dirk Behme
CC: Stefano Babic
CC: Fabio Estevam -
Apparently, CONFIG_SYS_HZ must be 1000. Change this, and fix the timer
driver to conform to this.Have the timer implementation export a custom API get_timer_us() for use
by the BCM2835 MMC API, which needs us resolution for a HW workaround.Signed-off-by: Stephen Warren
-
This fixes this build warning:
Configuring for qemu_mips64 - Board: qemu-mips64, Options: SYS_BIG_ENDIAN
text data bss dec hex filename
215344 13082 218720 447146 6d2aa qemu_mips64/u-boot
cfi_flash.c: In function 'flash_map':
cfi_flash.c:217:9: warning: cast to pointer from integer of different size [-Wint-to-pointer-cast]Signed-off-by: Stefan Roese
Cc: Tom Rini
