20 Dec, 2018
2 commits
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The HAB code can not set Field Return and SRK Revoke sticky bits in case
OCOTP CTRL clock is gated out.In case we disable OCOTP CTRL clock in DCD and plugin those features may
not operate as expected.Keep OCOTP CTRL clock enabled in DCD and plugin so HAB can propely lock
those features, users should use the CSF Unlock command to prevent those
features from being locked.Signed-off-by: Breno Lima
Reviewed-by: Ye Li
(cherry picked from commit 2ee4bd12140fa9a29ad1a7cb5016b78e4a4077f1) -
The HAB code can not set Field Return and SRK Revoke sticky bits in case
OCOTP CTRL clock is gated out.In case we disable OCOTP CTRL clock in DCD and plugin those features may
not operate as expected.Keep OCOTP CTRL clock enabled in DCD and plugin so HAB can propely lock
those features, users should use the CSF Unlock command to prevent those
features from being locked.Signed-off-by: Breno Lima
(cherry picked from commit fe78359704fa5c5199daf0274019ae58980bc710)
12 Dec, 2018
2 commits
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Write magic number in board early init, and clear magic when booting
Linux.This is to let XEN know the current EL1 code is U-Boot or Linux
when reset/reboot. This is just a workaround because CM41 could not
communicate with XEN now, even XEN knows that EL1 is reseting/rebooting.Signed-off-by: Peng Fan
Reviewed-by: Flynn xu
(cherry picked from commit 8132f6b5848d45cab795bb472d6484130985415d) -
To support partition reboot, the u-boot has to enable clocks by LPCG.
The LPCG will reset to default value only when the subsystem is totally
power off and reset. However, the resources in one subsystem may belong
to different partitions, so the partition reboot may not reboot the entire
subsystem.
Powers, clocks/lpcg, GPR, IP may not reset depends on various cases and
HW design. Thus, AP software has to ensure everything is reset by SW
itself to support such above cases.Signed-off-by: Ye Li
(cherry picked from commit 484104758d3c2f98d3c9ae493f778b1427e2630c)
20 Nov, 2018
1 commit
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Update the ddrc Qos setting for B1 to align with B0'ssetting.
Correct the initial clock for dram_pll. This setting will be
overwrite before ddr phy training. Although there is no impact
on the dram init, we still need to correct it to eliminate
confusion.Signed-off-by: Bai Ping
Reviewed-by: Ye Li
Tested-by: Robby Cai
(cherry picked from commit 566b798213ab9690966f163de2765acdbfe647a7)
12 Nov, 2018
6 commits
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- temp fix for boot hangup with camera
This reverts commit a8109598e7dca72d415ad5d26ac5868b88da9dfc.
Bug: 115532706
Test: test boot up
Change-Id: I7bb1bc14eb81ae0965fc03abdf5cb65444720d13 -
Add fastboot commands "fastboot oem at-get-vboot-unlock-challenge"
and "fastboot oem at-unlock-vboot" to support the authenticated
unlock feature for Android Things devices. Use software random
numbers generator to generate the 16 bytes random challenge, it
should be replaced with hardware encrypted random generator when
the TEE part is ready.Test: Generate unlock challenge by:
./avbtool make_atx_unlock_credential
--output=atx_unlock_credential.bin
--intermediate_key_certificate=atx_pik_certificate.bin
--unlock_key_certificate=atx_puk_certificate.bin
--challenge=my_generated_challenge.bin
--unlock_key=testkey_atx_puk.pem
validated the unlock credential successfully on imx7d_pico
and AIY.Change-Id: I4b8cee87c9e96924169479b65020a081136681f6
Signed-off-by: Ji Luo -
Trusty image should be loaded to different address for AIY 1G/3G ddr
board which have different ddr size. Use board id to distinguish
different baseboard, load trusty image to 0x7e00_0000 for AIY 1G ddr
board and 0xfe00_0000 for AIY 3G ddr board.Test: build and boot Trusty ok for AIY 1G/3G ddr board.
Change-Id: I62d8a19b13fe19f38075512a6faa4bbb36f74791
Signed-off-by: Ji Luo -
Because sysdeps.h in trusty include stdint.h, so we need to define
USE_STDINT.Test: Local build test and flash on imx7d. Verify provision som
key and product key succeed.
Bug: None
Change-Id: I08db7c10dd4453a87f15ff4432335fe4c41f9c5f -
for 1GB ram: cma=296M galcore.contiguousSize=8388608
for 3GB ram: cma=384M
Test: Boot successfully on AIY-1G & AIY-3GChange-Id: If082d5b751b5a5e06efe301c0b8e49ec4ac3dfb7
Signed-off-by: faqiang.zhu
Reviewed-on: http://androidsource.ap.freescale.net/project/5262
Reviewed-by: Wang Haoran
Signed-off-by: faqiang.zhu -
Set BUCK2 output for VDD_ARM to 0.85v
Set BUCK3 output for VDD_GPU off
Set BUCK4 output for VDD_VPU offChange-Id: I26b47b72ae6b8e714d12345b20324490f0947f56
Signed-off-by: faqiang.zhu
Reviewed-on: http://androidsource.ap.freescale.net/project/5177
Reviewed-by: zhang bo
07 Nov, 2018
1 commit
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The power domain driver is not ready when running board_early_init_f,
but we call it imx8qxp_gpmi_nand_initialize. so this cause u-boot reset
in early stage.Signed-off-by: Ye Li
Tested-by: Han Xu
03 Nov, 2018
7 commits
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Refact the i.MX8MQ dram init flow to reuse the common dram
driver used by i.MX8MM.Signed-off-by: Bai Ping
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Change the dram_pll_init function API to make it same
as i.MX8MM, so the dram init flow can use call the same
API for these two different SOC.Signed-off-by: Bai Ping
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Because u-boot USB gadget only can support one driver, so if we enable
ci_udc driver, the cdns3 gadget driver must be disabled. This cause build
error because we don't wrap the cdns gadget functions with its configuration.Fix the issue by adding CONFIG_USB_CDNS3_GADGET before cdns3 gadget function.
Signed-off-by: Ye Li
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Because the iMX8MQ DDR4 ARM2 has 4GB DDR. To fit new MMU settings, we split
it to two banks. The first bank has 3GB DDR, reach to 4GB memory map.
The second bank has 1GB DDR, is beyond 4GB memory map.Notice: there is no OPTEE for ARM2 board. The trust zone setting in OPTEE
for iMX8MQ EVK is not match with DDR size on ARM2 board. So ARM2 Only can
work without OPTEE.Signed-off-by: Ye Li
Reviewed-by: Peng Fan -
iMX8MM DDR3L validation board uses FPGA to link with SPI NOR flash
on ECSPI1 port. Update the codes and configurations to enable the
ECSPI1 to access SPI NOR in u-boot.Signed-off-by: Ye Li
Reviewed-by: Peng Fan -
Add implementation necessary for supporting SPL on QXP
ARM2 board with dynamic offset detection from container header.Signed-off-by: Teo Hall
-
The iMX7ULP B0 chip has added more pins for muxing USB ID. The A3 board
follows it to exploit PTC13 for USB ID, so we don't need to use GPIO
any longer. The USB driver can recognize the USB mode from USB PHY.After this change, old boards with design using GPIO for USB mode won't
be supported.Signed-off-by: Ye Li
27 Oct, 2018
1 commit
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enable CE_1 IOMUX setting for NAND on i.MX8MM EVK
Signed-off-by: Han Xu
25 Oct, 2018
2 commits
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Update the RFSHCTL3 config for DDR4.
Signed-off-by: Bai Ping
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Add DDR3 init codes, board codes, defconfig and DTS into u-boot.
Basic modules are ready: SD, UART, I2C, USB host and NAND.There is a FPGA on this board. It controls WDOG_B, and ENET PHY RESET.
So reset and ethernet won't work at default.Signed-off-by: Ye Li
Acked-by: Peng Fan
16 Oct, 2018
2 commits
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Add support for FIT image loading of ATF and uboot proper for iMX8QXP mek.
Signed-off-by: Abel Vesa
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Add support for FIT image loading of ATF and uboot proper for iMX8QM mek.
Signed-off-by: Abel Vesa
12 Oct, 2018
1 commit
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Update the DDR4 MR value on i.MX8MM DDR4 EVK board.
Signed-off-by: Bai Ping
Reviewed-by: Ye Li
11 Oct, 2018
1 commit
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The codes in imx8mq ARM2 SPL still return back to ROM when booting from
usb serial download. This is old way to support mfgtool not uuu.
Update the codes to support uuu when SPL SDP is enabled.Signed-off-by: Ye Li
01 Oct, 2018
2 commits
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Optimize the DDR4 init flow. Split the common flow
with the DDR specific timing config. So the common
flow can be reused.Signed-off-by: Bai Ping
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For LPDDR4 and DDR4, we use the same dram_timing struct
to config parameters. rename the 'lpddr4_timing' to
'dram_timing' for common use.Signed-off-by: Bai Ping
29 Sep, 2018
1 commit
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We enable the pull-up resistor for i2c pad by setting the PAD_CTL_PUE.
But this requires to enable pull resistors first by setting PAD_CTL_PE on iMX8MM,
otherwise the pull-up won't work.Signed-off-by: Ye Li
28 Sep, 2018
3 commits
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Allow iMX8QM mek SPL to boot from QSPI.
Signed-off-by: Abel Vesa
Reviewed-by: Ye Li -
Add spl implementation for iMX8QM MEK board.
Signed-off-by: Abel Vesa
Reviewed-by: Ye Li -
Add implementation for ARM2 LPDDR4 board
Signed-off-by: Teo Hall
20 Sep, 2018
2 commits
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Since we set the fdt_file value when running on iMX6ULZ. This
cause the saved fdt_file change be overwritten. So users can't
set to their own fdt_file.Signed-off-by: Ye Li
Reviewed-by: Peng Fan -
Since the mx6ulz don't have FEC, it needs to use USB2NET dongle
to connect network. We decouple the CONFIG_FEC_MXC with CONFIG_CMD_NET.
For 6ull, all defconfigs need to enable the CONFIG_FEC_MXC explicitly.Another change is adding ${usb_net_cmd} environment for usb start command
in netboot scripts on 6ulz.Signed-off-by: Ye Li
Reviewed-by: Peng Fan
18 Sep, 2018
2 commits
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Allow iMX8QXP SPL to boot from QSPI.
Signed-off-by: Abel Vesa
Reviewed-by: Ye Li -
Add SPL and u-boot support to load images from RAWNAND device when booting
from RAWNAND. The NAND SPL loads the FIT image from nandfit mtdpart at 64MB
offset of NAND. Users need uuu to burn the FIT image, kernel, DTB and rootfs
to all fixed mtdparts.Since NAND SPL needs large BSS and MALLOC size, this patch also moves the MALLOC
pool to DDR, and enable MALLOC_F pool on OCRAM for all malloc before DDR initialization.Signed-off-by: Ye Li
14 Sep, 2018
1 commit
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Add i.MX6ULZ support. the i.MX6ULZ is SW compatible
with i.MX6ULL. so most code of i.MX6ULL can be reused
by i.MX6ULZ.Signed-off-by: Bai Ping
12 Sep, 2018
1 commit
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Separate tcpc related operations with config CONFIG_USB_TCPC
so we can enable/disable this feature separately.Test: Boot ok on both imx8qm/8qxp_mek.
Change-Id: I46ef775e8deb4443944c0e969a4ced67c11ac48c
Signed-off-by: Luo Ji
11 Sep, 2018
1 commit
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Add DDR4 init codes, u-boot dtb and defconfig to support DDR4 EVK.
The DDR4 EVK removed eMMC and Flexspi, but use NAND instead. Current
codes support to boot from SD and enable NAND access in regular u-boot.Signed-off-by: Ye Li
Acked-by: Peng Fan
07 Sep, 2018
1 commit
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To support the uuu, pack the common qspi header with u-boot binary for
i.MX6/7 qspi u-boot.Signed-off-by: Han Xu