20 Nov, 2018
1 commit
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Update the ddrc Qos setting for B1 to align with B0'ssetting.
Correct the initial clock for dram_pll. This setting will be
overwrite before ddr phy training. Although there is no impact
on the dram init, we still need to correct it to eliminate
confusion.Signed-off-by: Bai Ping
Reviewed-by: Ye Li
Tested-by: Robby Cai
(cherry picked from commit 566b798213ab9690966f163de2765acdbfe647a7)
03 Nov, 2018
1 commit
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Refact the i.MX8MQ dram init flow to reuse the common dram
driver used by i.MX8MM.Signed-off-by: Bai Ping
03 Sep, 2018
1 commit
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enhance memory controller performance and QoS setting
Signed-off-by: Tom.zheng
Signed-off-by: Bai Ping
Reviewed-by: Jian Li
(cherry picked from commit ae7b37d3ed72bad542c8e77db4bbc0325180d6d2)
21 Aug, 2018
1 commit
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Currently the SRAM is allocated to malloc pool due to large malloc needed
by USB SDP. The stack is moved to OCRAM. This causes a problem when enabling
HAB. The HAB authentication needs large memory on stack, so after ATF image loaded,
the stack overwrites the ATF image in OCRAM and causes authentication failed.This patch moves the malloc pool to DDR and set back stack to SRAM. So SDP still
can run with enough memory on DDR. And the stack overwrite issue can be fixed by
enough memory 24KB left on SRAM.This change also need to use a early malloc pool by defining the CONFIG_MALLOC_F_ADDR.
And in SPL codes, we have to adjust DDR init before board_init_r.Signed-off-by: Ye Li
20 Aug, 2018
1 commit
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Add 1G DDR support, distinguish different boards by the
Board ID, They are:
SAI5_MCLK: Board_id[6]
SAI5_RXFS: Board_id[5]
SAI5_RXC: Board_id[4]
SAI5_RXD3: Board_id[3]
SAI5_RXD2: Board_id[2]
SAI5_RXD1: Board_id[1]
SAI5_RXD0: Board_id[0]
Current Board ID for imx8m boards are:
AIY Micron 1G: 0x5c
AIY Hynix 1G: 0x56
AIY Mirconb 3G: 0x40
Wibo 3G: 0x00
imx8m_ref 3G: 0x00Test: Boot ok on all imx8m boards.
Change-Id: I3d65931483f369c545632b660f04fc9da120547d
Signed-off-by: Luo Ji
Reviewed-on: http://androidsource.ap.freescale.net/project/5093
Reviewed-by: guoyin.chen
Reviewed-by: Wang Haoran
17 Aug, 2018
1 commit
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Since the u-boot gadget class drivers don't support super speed, if
we set DWC3 gadget driver to super speed, the device mode will meet problem
when using USB3.0 cable. So force the DWC3 gadget driver to high speed
for both SPL and regular u-boot.Signed-off-by: Ye Li
11 Aug, 2018
2 commits
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As there is problem with super speed with SDP, we force the dwc3
usb speed to be high speed.Signed-off-by: Li Jun
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Enable DWC3 USB support at i.MX850D platform
Signed-off-by: Frank Li
13 Jun, 2018
1 commit
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Add board level support for android and android auto. Each board has
android/andriod_auto specified header file for defining relevant configuraitons.
And add build targets for their android uboot images building.Signed-off-by: Ye Li
27 Apr, 2018
4 commits
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Adding basic display support for splash screen.
Signed-off-by: Oliver Brown
Signed-off-by: Ye Li
(cherry picked from commit 31058332c273d181390560ae2b88209b628f5842) -
Add 400Mhz, 600Mhz and 800Mhz frequencies for dram pll init function to
support DDR3L/DDR4/LPDDR4.Signed-off-by: Ye Li
(cherry picked from commit 0e9dbe4f74fdc0fae1acd8ad5b75815c28286be1) -
i.MX8MQ EVK has two USB ports, the port 0 is typec, the port 1 is host.
This patch enables both device and host mode (xhci) for typec port by setting tcpc
to relevant UFP/DFP mode. For port 1, it is only supports the host mode (xhci).PD charge is enabled at default on typec port for the dead battery. In this case,
the typec port only works in device mode.Signed-off-by: Ye Li
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Add board level codes and build config for i.MX8MQ EVK board.
Support SPL to initialize the DDR and load u-boot.Signed-off-by: Ye Li