19 Feb, 2014
9 commits
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This shows the log obtained while testing qspi on AM437x board.
Signed-off-by: Sourav Poddar
Reviewed-by: Jagannadha Sutradharudu Teki -
Without this delay, write/read is failing.
Looks like, the WIP always remain set and hence a timeout
occurs leading to the error.Without this patch, device does not get probed also.
Here is the log.U-Boot#
U-Boot#
U-Boot#
U-Boot# sf probe 0
SF: Unsupported flash IDs: manuf ff, jedec ffff, ext_jedec ffff
Failed to initialize SPI flash at 0:0
U-Boot# sf probe 0While with this patch, log is
U-Boot# sf probe 0
SF: Detected MX25L51235F with page size 256 Bytes, erase size 64 KiB, total 64 MiB, mapped at 30000000
U-Boot# sf erase 0 0x80000
SF: 524288 bytes @ 0x0 Erased: OK
U-Boot# mw 81000000 0xdededede 0x40000
U-Boot# sf write 81000000 0 0x40000
SF: 262144 bytes @ 0x0 Written: OK
U-Boot# sf read 82000000 0 0x40000
SF: 262144 bytes @ 0x0 Read: OK
U-Boot# md 0x82000000Signed-off-by: Sourav Poddar
Reviewed-by: Jagannadha Sutradharudu Teki -
Add AM43xx specific changes.
Signed-off-by: Sourav Poddar
Reviewed-by: Jagannadha Sutradharudu Teki -
Enables support for SPI SPL, QSPI and Spansion serial flash device
on the EVM. Configures pin muxes for QSPI mode.Signed-off-by: Sourav Poddar
Reviewed-by: Jagannadha Sutradharudu Teki -
Add QSPI definitions and clock configuration support.
Signed-off-by: Sourav Poddar
Reviewed-by: Jagannadha Sutradharudu Teki -
The dual lite and solo variant have only 4 SPI controller.
respect this in the MXC_SPI_BASE_ADRESSES macroSigned-off-by: Markus Niebel
Reviewed-by: Jagannadha Sutradharudu Teki -
SPI_MODE_3 requires clk high when inactive. The SCLK_CTL
field of the config reg was not configured in case of CPOL.
Fix configuration so that SPI_MODE_3 which uses CPOL configures
the clk line to be high in inactive state.Signed-off-by: Markus Niebel
Reviewed-by: Jagannadha Sutradharudu Teki -
Provide define for the SCLK_CTL field of the config reg of ECSPI.
While at it, oder the defines to improve readability and make
adding more defines easier.Signed-off-by: Markus Niebel
Reviewed-by: Jagannadha Sutradharudu Teki -
Timeout calculation should be out of the data loop.
This patch increase spi bandwidth for 30%.Signed-off-by: Michal Simek
Reviewed-by: Jagannadha Sutradharudu Teki
08 Feb, 2014
1 commit
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Driver for non-standard on-chip UART, instantiated in the ARC (Synopsys)
FPGA Boards such as ARCAngel4/ML50xSigned-off-by: Alexey Brodkin
Cc: Mischa Jonker
Cc: Francois Bedard
Cc: Tom Rini
Cc: Wolfgang Denk
Cc: Stefano Babic
07 Feb, 2014
20 commits
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Now that the designware ethernet driver uses phylib we need to turn it
on here.Acked-by: Stefan Roese
Signed-off-by: Tom Rini -
Up until now this driver only worked with data cache disabled.
To make it work with enabled data cache following changes were required:* Flush Tx/Rx buffer descriptors their modification
* Invalidate Tx/Rx buffer descriptors before reading its values
* Flush cache for data passed from CPU to GMAC
* Invalidate cache for data passed from GMAC to CPUCc: Joe Hershberger
Cc: Vipin Kumar
Cc: Stefan Roese
Cc: Mischa Jonker
Cc: Shiraz Hashim
Cc: Albert ARIBAUD
Cc: Amit Virdi
Cc: Sonic Zhang
Signed-off-by: Alexey Brodkin -
With this change driver will benefit from existing phylib and thus
custom phy functionality implemented in the driver will go away:
* Instantiation of the driver is now much shorter - 2 parameters
instead of 4.
* Simplified phy management/functoinality in driver is replaced with
rich functionality of phylib.
* Support of custom phy initialization is now done with existing
"board_phy_config".Note that after this change some previously used config options
(driver-specific PHY configuration) will be obsolete and they are simply
substituted with similar options of phylib.For example:
* CONFIG_DW_AUTONEG - no need in this one. Autonegotiation is enabled
by default.
* CONFIG_DW_SEARCH_PHY - if one wants to specify attached phy
explicitly CONFIG_PHY_ADDR board config option has to be used, otherwise
automatically the first discovered on MDIO bus phy will be usedI believe there's no need now in "doc/README.designware_eth" because
user only needs to instantiate the driver with "designware_initialize"
whose prototype exists in "include/netdev.h".Cc: Joe Hershberger
Cc: Vipin Kumar
Cc: Stefan Roese
Cc: Mischa Jonker
Cc: Shiraz Hashim
Cc: Albert ARIBAUD
Cc: Amit Virdi
Cc: Sonic Zhang
Signed-off-by: Alexey Brodkin -
In "common/Makefile" "miiphyutil.o" gets built if any of the following
items enabled:
* CONFIG_PHYLIB
* CONFIG_MII
* CONFIG_CMD_MIISo it's possible to not define CONFIG_MII or CONFIG_CMD_MII and still
use functions like "miiphy_get_dev_by_name".In its turn "miiphy_get_dev_by_name" traverses "mii_devs" list which is
not initialized because "miiphy_init" never got called.Cc: Rob Herring
Cc: Simon Glass
Cc: Wolfgang Denk
Acked-by: Joe Hershberger
Signed-off-by: Alexey Brodkin -
Driver "init" function might be called multiple times.
On every "init" Tx/Rx buffer descriptors are initialized: "descs_init"
-> "{tx|rx}_descs_init".In its turn those init functions set MAC's "{tx|rx}desclistaddr" to
point on the first buffer descriptor in the list.So CPU to start operation from the first buffer descriptor as well after
every "init" we have to reset "{tx|rx}_currdescnum".Cc: Joe Hershberger
Cc: Vipin Kumar
Cc: Stefan Roese
Cc: Mischa Jonker
Signed-off-by: Alexey Brodkin -
Signed-off-by: Alexey Brodkin
Cc: Vineet Gupta
Cc: Francois Bedard
Cc: Wolfgang Denk
Cc: Heiko Schocher -
Signed-off-by: Alexey Brodkin
Cc: Vineet Gupta
Cc: Francois Bedard
Cc: Wolfgang Denk
Cc: Heiko Schocher -
AXS101 is a new generation of devlopment boards from Synopsys that houses
ASIC with ARC700 and lots of DesignWare peripherals:* DW APB UART
* DW Mobile Storage (MMC/SD)
* DW I2C
* DW GMACSigned-off-by: Alexey Brodkin
Cc: Vineet Gupta
Cc: Francois Bedard
Cc: Wolfgang Denk
Cc: Heiko Schocher -
Arcangel4 is a FPGA-based development board that is used for prototyping and
verificationof of both ARC hardware (CPUs) and software running upon CPU.This board avaialble in 2 flavours:
* Little-endian (arcangel4)
* Big-endian (arcangel4-be)Signed-off-by: Alexey Brodkin
Cc: Vineet Gupta
Cc: Francois Bedard
Cc: Wolfgang Denk
Cc: Heiko Schocher -
Signed-off-by: Alexey Brodkin
Cc: Vineet Gupta
Cc: Francois Bedard
Cc: Wolfgang Denk
Cc: Heiko Schocher -
Signed-off-by: Alexey Brodkin
Cc: Vineet Gupta
Cc: Francois Bedard
Cc: Wolfgang Denk
Cc: Heiko Schocher -
These are library functions used by ARC700 architecture.
Signed-off-by: Alexey Brodkin
Cc: Vineet Gupta
Cc: Francois Bedard
Cc: Wolfgang Denk
Cc: Heiko Schocher -
Signed-off-by: Alexey Brodkin
Cc: Vineet Gupta
Cc: Francois Bedard
Cc: Wolfgang Denk
Cc: Heiko Schocher -
These are header files used by ARC700 architecture.
Also note that "arch-arc700/hardware.h" is only required for compilation of
"designware_i2c" driver which refers to "asm/arch/hardware.h".
It would be good to fix mentioned driver sometime soon but it will cause
changes in ARM board configs that use "designware_i2c".Signed-off-by: Alexey Brodkin
Cc: Vineet Gupta
Cc: Francois Bedard
Cc: Wolfgang Denk
Cc: Heiko Schocher -
EMAC_VLANx regs is not properly initiallized in u-boot, once it's overwrite in the
kernel when DSA enabled, hot reset will lead to bringing up EMAC fail in u-boot.Signed-off-by: Aaron Wu
Signed-off-by: Sonic Zhang -
Signed-off-by: Sonic Zhang
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Signed-off-by: Bob Liu
Signed-off-by: Sonic Zhang -
Signed-off-by: Sonic Zhang
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With e0059ea switching to using SZ_1K, we need to #include
here for everyone to build still.Signed-off-by: Tom Rini
06 Feb, 2014
9 commits
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Just extend tables with this new device.
Signed-off-by: Michal Simek
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When ARCH_DMA_MINALIGN is greater than header size of the bit file, and buf is
not aligned, new_buf address became greater then buf_start address and the
load_word loop corrupts bit file data.A work around is to decrease new_buf of ARCH_DMA_MINALIGN, it might corrupt data
before buf but permits to load correctly.Signed-off-by: Stany MARCEL
Signed-off-by: Michal Simek -
The mv_udc is not marvell-specific anymore. The mv_udc is used to drive
generic ChipIdea CI13xxx series OTG cores, so rename the driver to ci_udc
instead.Signed-off-by: Marek Vasut
Cc: Eric Nelson
Cc: Stefano Babic -
Apparently debug memset (with a 0x55 value) has been overlooked in the
f_thor code.Signed-off-by: Lukasz Majewski
Cc: Marek Vasut -
Now it is possible to allocate static request - which receives data from
the host (OUT transaction) to the size of THOR packet.Signed-off-by: Lukasz Majewski
Cc: Marek Vasut -
The Samsung's UDC driver is not anymore copying data from USB requests to
aligned internal buffers. Now it works directly in data allocated in the
upper layers like UMS, DFU, THOR.This change is possible since those gadgets now must take care to allocate
buffers aligned to cache line (CONFIG_SYS_CACHELINE_SIZE).This can be achieved by using DEFINE_CACHE_ALIGN_BUFFER() or
ALLOC_CACHE_ALIGN_BUFFER() macros. Those take care to allocate buffer
aligned to cache line in both starting address and its size.
Sometimes it is enough to just use memalign() with size being a
multiplication of cache line size.Test condition
- test HW + measurement: Trats - Exynos4210 rev.1
- test HW Trats2 - Exynos4412 rev.1
400 MiB compressed rootfs image download with `thor 0 mmc 0`Measurement:
Transmission speed: 27.04 MiB/sSigned-off-by: Lukasz Majewski
Cc: Marek Vasut -
This patch removed obscure restriction on the HW setting of DMA transfers.
Before this change each transaction sent up to 512 bytes (with packet count
equal to 1) for non EP0 transfer.Now it is possible to setup DMA transaction up to DMA_BUFFER_SIZE.
Test condition
- test HW + measurement: Trats - Exynos4210 rev.1
- test HW Trats2 - Exynos4412 rev.1
400 MiB compressed rootfs image download with `thor 0 mmc 0`Measurement:
Transmission speed: 20.74 MiB/sSigned-off-by: Lukasz Majewski
Cc: Marek Vasut -
A set of cache operations (both invalidation and flush) were redundant
in the S3C HS OTG Samsung driver:1. s3c_udc_ep0_zlp - to transmit EP0's ZLP packets one don't need to flush
the cache (since it is the zero length transmission)2. s3c_udc_pre_setup and s3c_ep0_complete_out - cache invalidation is not
needed when the buffer for OUT EP0 transmission is setup, since no data
has yet arrived.Cache cleanups presented above don't contribute much to transmission speed
up, hence shall be regarded as cosmetic changes.3. setdma_rx - here the s3c UDC driver's internal buffers were invalidated.
This call is not needed anymore since we reuse the buffers passed from
gadgets. This is a key contribution to transmission speed improvement.Test condition
- test HW + measurement: Trats - Exynos4210 rev.1
- test HW Trats2 - Exynos4412 rev.1
400 MiB compressed rootfs image download with `thor 0 mmc 0`Measurements:
Base values (without improvement):
Transmission speed: 9.51 MiB/sAfter the change:
Transmission speed: 10.15 MiB/sSigned-off-by: Lukasz Majewski
Cc: Marek Vasut -
Calls to malloc() have been replaced by memalign. It now provides proper
buffer alignment.Signed-off-by: Lukasz Majewski
Cc: Marek Vasut
05 Feb, 2014
1 commit
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Signed-off-by: Tom Rini