19 Dec, 2014
12 commits
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There are two standard SD card slots on the Crown Bay board, which
are connected to the Topcliff PCH SDIO controllers. Enable the SDHC
support so that we can use them.Signed-off-by: Bin Meng
Acked-by: Simon Glass -
The Crown Bay board has an SST25VF016B flash connected to the Tunnel
Creek processor SPI controller used as the BIOS media where U-Boot
is stored. Enable this flash support.Signed-off-by: Bin Meng
Acked-by: Simon Glass -
Signed-off-by: Bin Meng
Acked-by: Simon Glass -
Signed-off-by: Bin Meng
Acked-by: Simon Glass -
Signed-off-by: Bin Meng
Acked-by: Simon Glass -
Intel Tunnel Creek GPIO register block is compatible with current
ich6-gpio driver, except the offset and content of GPIO block base
address register in the LPC PCI configuration space are different.Use u16 instead of u32 to store the 16-bit I/O address of the GPIO
registers so that it could support both Ivybridge and Tunnel Creek.Signed-off-by: Bin Meng
Acked-by: Simon Glass -
To avoid having two microcode formats, adjust the build system to support
obtaining the microcode from the device tree, even in the case where it
must be made available before the device tree can be accessed.Signed-off-by: Simon Glass
Reviewed-by: Bin Meng
Tested-by: Bin Meng -
Implement minimum required functions for the basic support to
queensbay platform and crownbay board.Currently the implementation is to call fsp_init() in the car_init().
We may move that call to cpu_init_f() in the future.Signed-off-by: Bin Meng
Acked-by: Simon Glass -
Integrate the processor microcode version 1.05 for Tunnel Creek,
CPUID device 20661h.Signed-off-by: Bin Meng
Acked-by: Simon Glass -
There are several problems in the code. The device tree decode is incorrect
in ways that are masked due to a matching bug. Both are fixed. Also
microcode_read_rev() should be inline and called before the microcode is
written.Note: microcode writing does not work correctly on ivybridge for me. Further
work is needed to resolve this. But this patch tidies up the existing code
so that will be easier.Signed-off-by: Simon Glass
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There are new microcode revisions available. Update them. Also change
the format so that the first 48 bytes are not omitted from the device tree
data.Signed-off-by: Simon Glass
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We might end up with a few of these, so put them in their own directory.
Signed-off-by: Simon Glass
Reviewed-by: Bin Meng
18 Dec, 2014
3 commits
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Now UniPhier platform is only supported with SPL.
Signed-off-by: Masahiro Yamada
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init_page_table is only set on SPL.
Signed-off-by: Masahiro Yamada
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The property name of the "aliases" node should be "serial*"
to assign a desired number for the device sequence number.Signed-off-by: Masahiro Yamada
17 Dec, 2014
1 commit
16 Dec, 2014
4 commits
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Offsets were overlaping, causing pamu access violations in
hypervised scenarios.Signed-off-by: Cristian Sovaiala
Signed-off-by: Laurentiu Tudor
Reviewed-by: York Sun -
Not all portals might be managed and therefore visible.
Set the isdr register so that the corresponding isr register
won't be set. This is required when supporting power management.Signed-off-by: Jeffrey Ladouceur
Reviewed-by: York Sun -
Commit f29f804a93e87c17670607641d120f431a3b0633 generalized the TLB
mapping function, but made the DDR mapping leftover size to zero,
causing the message not printed.Signed-off-by: York Sun
CC: Alexander Graf
CC: Scott Wood
15 Dec, 2014
1 commit
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Commit 65dd74a674d6 (x86: ivybridge: Implement SDRAM init) introduced
x86-specific asmlinkage into arch/x86/include/asm/config.h.Commit ed0a2fbf14f7 (x86: Add a definition of asmlinkage) added the
same macro define again, this time, into include/common.h.
(Please do not add arch-specific stuff to include/common.h any more;
it is already too cluttered.)The generic asmlinkage is defined in . If you want
to override it with an arch-specific one, the best way is to add it
to like Linux Kernel.Signed-off-by: Masahiro Yamada
Cc: Simon Glass
Tested-by: Simon Glass
14 Dec, 2014
10 commits
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FSP builds a series of data structures called the Hand-Off-Blocks
(HOBs) as it progresses through initializing the silicon. These data
structures conform to the HOB format as described in the Platform
Initialization (PI) specification Volume 3 Shared Architectual
Elements specification, which is part of the UEFI specification.Create a simple command to parse the HOB list to display the HOB
address, type and length in bytes.Signed-off-by: Bin Meng
Acked-by: Simon Glass -
Per Intel FSP architecture specification, FSP provides 3 routines
for bootloader to call. The first one is the TempRamInit (aka
Cache-As-Ram initialization) and the second one is the FspInit
which does the memory bring up (like MRC for other x86 targets)
and chipset initialization. Those two routines have to be called
before U-Boot jumping to board_init_f in start.S.The FspInit() will return several memory blocks called Hand Off
Blocks (HOBs) whose format is described in Platform Initialization
(PI) specification (part of the UEFI specication) to the bootloader.
Save this HOB address to the U-Boot global data for later use.Signed-off-by: Bin Meng
Acked-by: Simon Glass -
Signed-off-by: Bin Meng
Acked-by: Simon Glass -
Use inline assembly codes to call FspNotify() to make sure parameters
are passed on the stack as required by the FSP calling convention.Signed-off-by: Bin Meng
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This is the initial import from Intel FSP release for Queensbay
platform (Tunnel Creek processor and Topcliff Platform Controller
Hub), which can be downloaded from Intel website.For more details, check http://www.intel.com/fsp.
Note: U-Boot coding convention was applied to these codes, so it
looks completely different from the original Intel release.
Also update FSP support codes license header to use SPDX ID.Signed-off-by: Bin Meng
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On most x86 boards, the legacy serial ports (io address 0x3f8/0x2f8)
are provided by a superio chip connected to the LPC bus. We must
program the superio chip so that serial ports are available for us.Signed-off-by: Bin Meng
Acked-by: Simon Glass -
Signed-off-by: Bin Meng
Acked-by: Simon Glass -
Movie setup_pch_gpios() in the ich6-gpio driver to the board support
codes, so that the driver does not need to know any platform specific
stuff (ie: include the platform specifc chipset header file).Signed-off-by: Bin Meng
Acked-by: Simon Glass -
Move GD_BIST from lib/asm-offsets.c to arch/x86/lib/asm-offsets.c
as it is x86 arch specific stuff. Also remove GENERATED_GD_RELOC_OFF
which is not referenced anymore.Signed-off-by: Bin Meng
Acked-by: Simon Glass -
Currently the ROM_SIZE is hardcoded to 8MB in arch/x86/Kconfig. This
will not be the case when adding additional board support. Hence we
make ROM_SIZE configurable (512KB/1MB/2MB/4MB/8MB/16MB) and have the
board Kconfig file select the default ROM_SIZE.Signed-off-by: Bin Meng
Acked-by: Simon Glass
12 Dec, 2014
9 commits
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Conflicts:
board/freescale/mx6sxsabresd/mx6sxsabresd.cSigned-off-by: Tom Rini
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This converts all Tegra boards over to use driver model for I2C. The driver
is adjusted to use driver model and the following obsolete CONFIGs are
removed:- CONFIG_SYS_I2C_INIT_BOARD
- CONFIG_I2C_MULTI_BUS
- CONFIG_SYS_MAX_I2C_BUS
- CONFIG_SYS_I2C_SPEED
- CONFIG_SYS_I2CThis has been tested on:
- trimslice (no I2C)
- beaver
- Jetson-TK1It has not been tested on Tegra 114 as I don't have that board.
Acked-by: Heiko Schocher
Signed-off-by: Simon Glass -
Nyan-big is a Tegra124 clamshell board that is very similar to venice2, but
it has a different panel, the sdcard cd and wp sense are flipped, and it has
a different revision of the AS3722 PMIC.This is the Acer Chromebook 13 CB5-311-T7NN (13.3-inch HD, NVIDIA
Tegra K1, 2GB). The display is not currently supported, so it should
boot on other nyan-based Chromebooks also, but only the device tree for
nyan-big is provided here.The device tree file is from Linux but with features removed which are
unlikely to be supported in U-Boot soon (regulators, pinmux). Also the
addresses are updated to 32-bit.Signed-off-by: Allen Martin
Signed-off-by: Simon Glass
(rebase, change to 'nyan-big', fix pinmux that resets nyan-big) -
Sync this up with Linux v3.18-rc5. Exclude features that are unlikely to
supported in U-Boot soon (regulators, pinmux). Also the addresses are
updated to 32-bit. Otherwise it is the same. Also bring in the dt-bindings
for pinctrl.Signed-off-by: Simon Glass
Acked-by: Stephen Warren -
This will be used by nyan-big, but bring it in in a separate patch since it
will be common to other boards.Signed-off-by: Simon Glass
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Add an I2C bus to the device tree, with an EEPROM emulator attached to one
of the addresses.Signed-off-by: Simon Glass
Acked-by: Heiko Schocher
Reviewed-by: Masahiro Yamada -
To enable testing of I2C, add a simple I2C EEPROM simulator for sandbox.
It supports reading and writing from a small data store.Signed-off-by: Simon Glass
Acked-by: Heiko Schocher
Reviewed-by: Masahiro Yamada
