04 Mar, 2016
2 commits
-
To simplify kernel clock management, we switch to use DRAM_PLL for
DRAM controller and DDR PHY, but not use DRAM_ALT_CLK_ROOT.Signed-off-by: Peng Fan
-
On i.MX7D TO1.1, design team adds a mux cell at the CKE path to fix the suspend
mode reset issue, but seems it add extra delay on CKE path, so CKE-CK timing violated.
When DDR enters self-refresh or retention for long time(> 15seconds per testing on some boards),
DDR data corruption occured, not able to decrease CKE delay, so we have to add extra
delay on all other signals to balance it.
DDR script needs to be fine-tuned according to this hardware change.For DDR3, since the timing margin is not good, we have to decrease the DDR frequency from
533Mhz to 400Mhz.Compass link:
http://compass.freescale.net/livelink/livelink?func=ll&objid=235010235&objAction=browse&sort=nameTest:
Overnight tests passed on all changed boards.Signed-off-by: Ye Li
17 Jun, 2015
1 commit
-
Abstracted the CSF size in imximage from a hardcoded value to a config
setting CONFIG_CSF_SIZE. This configuration is only enabled for secure
boot.
Increased the size of the CSF default allocation to 0x4000. This size
covers the event the worst case of 4906-bits keys.
29 Apr, 2015
1 commit
-
* Add mx7d_12x12_ddr3_arm2 target board support
* Initial support for mx7d_12x12_ddr3_arm2 target
board add support for base hardware eMMC, SD and
ECSPI boot.Signed-off-by: Adrian Alonso
Signed-off-by: Ye.Li
(cherry picked from commit 51d69f7996cc6e6da8bb3f0af751549cb2435e44)Conflicts:
boards.cfg
