27 Apr, 2018
40 commits
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Update DM PMIC settings and LDO bypass support.
Add BMODE support.
Add LVDS and LCD splash screen support
Add two ethernet controller support
Update environment settings
Add plugin supportSigned-off-by: Ye Li
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Copy the DTS from v2017.03
Compared with kernel DTS, the changes in DTS for u-boot:
1. To support DM QSPI driver, modify the n25q256a flash node's compatible
to "spi-flash".
2. Add pin settings for supporting i2c bus force idle.Signed-off-by: Ye Li
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Update mx6sxsabresd defconfig to align with v2017.03 with DM SPI and
DM ethernet enabled.Add other configs to support QSPI2 boot, reworked eMMC, M4 fastboot and
plugin.Signed-off-by: Ye Li
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Add emmc support which needs board rework.
Add I2C2.
Update DM PMIC settings and LDO bypass support.
Add BMODE support.
Add LVDS and LCD splash screen support
Add PCI power and reset GPIO and disable PCI at default.
Update QSPI settings for QSPI boot and M4 fastup.
Update environment settingsSigned-off-by: Ye Li
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Update i.MX6SX dtsi file and relevant DTS header files.
Add the imx6sx-sdb-emmc DTS file for reworked eMMC board.Changes in DTS and DTSi:
1. Modify the n25q256a flash node's compatible to "spi-flash".
2. Add spi0 and spi1 alias for qspi1 and qspi2.
3. Add USB alias
4. Remove MMC aliasSigned-off-by: Ye Li
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Add config files to support NAND and QSPI boot.
Add config file for plugin.
Add config files for RevA board and RevB boards.
Update settings to enable DM ethernet driver, remove the SYS_TEXT_BASESigned-off-by: Ye Li
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1. Add plugin support
2. Update to latest ddr3 script v2.0 version
refer commit (b4db09bc0fc96e7c7461afade6346e0700ad582f)
3. Add ddr3 script for TO1.1
4. Add BMODE support
5. Update header files to support QSPI boot and NAND boot settings.
6. Remove the wdog WCR bit 4 clear. Since we have implemented reset_cpu for mx7d.Signed-off-by: Ye Li
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Porting the the imx7d dtsi, dts files and binding files from kernel
(f3834c73366f985fef6c1fdaaa129dfceb6151cb)New dts files are added to support GPMI-WEIM, QSPI, RevA boards.
Changes in DTS and DTSi:
1. Add USB alias
2. Modify the SPI alias for qspi
3. Disable USDHC2 since it is for SDIO
4. Add i2c force idle support pins
5. Add LPSR pinfunc file
6. Removed mmc alias. So that device id in DM-MMC is aligned with Non-DM MMC.Signed-off-by: Ye Li
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Update LCD setup codes to use the parameters structure used for all
i.mx platforms, discard to use videmode environment variable.Signed-off-by: Ye Li
(cherry picked from commit 3b0609ca267baaf6a78bebaccc6896e6508d1844) -
Add epdc support from v2016.03.
Add a epdc specified DTS file for using epdcSigned-off-by: Peng Fan
Signed-off-by: Ye Li
(cherry picked from commit ab2f9e136f5da034a8335dc8ca276a54367132e8) -
Add FEC2 and convert to use FEC DM driver.
Add board rev check.Signed-off-by: Peng Fan
Signed-off-by: Ye Li
(cherry picked from commit 0137915ed40e2da5a6de4d30574d08e2bf3a0363) -
The issue on the i.MX7D is that, there is one cache-able memory access
between the L1 and L2 cache flush by calling the flush_dache_all->
v7_maint_dcache_all() [Flush L1 and L2 cache) which written in the C code.L1-cache-flush -> This will flush L1 cache to L2 cache in the end.
Cache-able memory access -> This will have the chance cause the L1 line-fill
with dirty data from L2 cache(L1 cache-line dirty,
L2 clean)
L2-cache-flush -> This will only flush L2 cache to L3, but still
some dirty data on the L1 cacheline.After C & M bit clean, -> The dirty data on the L1 cache line lost, which will
cause memory coherent issue if that dirty cache line
has some useful dataThis patch should works fine on the i.MX6 and i.MX7.
The second cache flush have zero impact on the i.MX6, but this is really need for
the i.MX7D platform due to the L1 line-fill during the first dcache_flush.And the second flush will not bring in the L1 dirty cache line due to the C bit is
clear now, which means the dcache is disabled.Acked-by: Jason Liu
Reviewed-by: Jason Liu
Signed-off-by: Ye.Li
(cherry picked from commit f5d5f07fba936c4bb05c887de9d72fb75b3dc0f2)
(cherry picked from commit 86c784cf4c4b633d37a76de7d47155c08f75dc82)
(cherry picked from commit d85cd484e6825631aa1ab572e5e0539f2191d795)
(cherry picked from commit 2b29c1873c2293abe1c4b361392521223b9c9ecf)
(cherry picked from commit 3eaf56494f3000f841531e8c219cf3dd9ca024f7) -
According to the Cortex-A7 TRM, for ACTLR.SMP bit "You must ensure this bit
is set to 1 before the caches and MMU are enabled, or any cache and TLB
maintenance operations are performed".
ROM sets this bit in normal boot flow, but when in serial download mode, it is not set.
Here we add it in u-boot as a common flow for all i.MX cortex-a7 platforms,
including mx7d, mx6ul/ull and mx7ulp.Signed-off-by: Ye Li
(cherry picked from commit 14990af03450f3e1898135c86fd8b93328007617)
(cherry picked from commit 79e968112ebeeb4c656263a434f6fbffc8f533d9) -
This EPDC/EPXP QoS setting is needed for EPDC stress test to pass.
Signed-off-by: Robby Cai
Signed-off-by: Peng Fan
(cherry picked from commit 1b32518d1c27f05eb84a4cb93594710354b2e343)
(cherry picked from commit 8fd2dbe9097b09715f84e1c0c17dcd6a6351fb35) -
-Change HDMI video mode to VGA.
-Add pixel clock fraction part setting in IPU driver,
fix video mode timing issue.
-Add overflow state clear workaround,
fix kernel hang in HDMI driver issue.
-Correct IPU clock to 264MHz.Signed-off-by: Sandor Yu
Signed-off-by: Nitin Garg
Signed-off-by: Peng Fan
Signed-off-by: Ye Li
(cherry picked from commit 5028519b434d5dfbe53c48ac4b115ff8b69bbac7)
(cherry picked from commit 8dcbd43b971616fb67dc3b2af32e2d33f68ed0ce) -
This patch adds enable/disable hooks support for ldb_di[0/1] clocks
and enables/disables them when necessary.Signed-off-by: Liu Ying
(cherry picked from commit 615d4c51679a6c2ee0ed4c5e3922eec76646eef1)
(cherry picked from commit 152192507c3bbaba093783d7da32b88327705c63)
(cherry picked from commit 036b71e1cd77ddb1827fd85eb7035fb7eccb7b12) -
The LDB is found in MX6 variants and MX53, so this patch makes the ldb_di clock
relevant code be built only for them.Signed-off-by: Liu Ying
(cherry picked from commit 3e40c7466ae7d1d6ca74011bfe69ae059d412a3b)
(cherry picked from commit 0c47d4138fd2fe8aa864160e23428b2ef95f16ae)
(cherry picked from commit a59c901317e70da111b426db1be77f289eccbcbc) -
The i.MX7ulp EVK board uses GPIO to detect ID for USB OTG0,
but when using DM USB driver, it is hard coded to use OTG ID pin.
Add a board override function that when extcon property is provided,
the function can check the GPIO to get ID.Signed-off-by: Ye Li
(cherry picked from commit 8382781a59fbae1d8ab797d64761136277e291d1) -
When doing port reset, the PR bit of PORTSC1 will be automatically
cleared by our IP, but standard EHCI needs explicit clear by software. The
EHCI-HCD driver follow the EHCI specification, so after 50ms wait, it
clear the PR bit by writting to the PORTSC1 register with value loaded before
setting PR.This sequence is ok for our IP when the delay time is exact. But when the timer
is slower, some bits like PE, PSPD have been set by controller automatically
after the PR is automatically cleared. So the writing to the PORTSC1 will overwrite
these bits set by controller. And eventually the driver gets wrong status.We implement the powerup_fixup operation which delays 50ms and will check
the PR until it is cleared by controller. And will update the reg value which is written
to PORTSC register by EHCI-HCD driver. This is much safer than depending on the delay
time to be accurate and aligining with controller's behaiver.Signed-off-by: Ye Li
(cherry picked from commit 8dfdf83abaff44efb487f801cd1757a729d427c5)
(cherry picked from commit cafc860907a408156a43fa20169dfc187648618e) -
The ULP has two USB controllers. These two controllers have similar NC
registers layout as i.MX7D. But OTG0 uses UTMI PHY simliar as i.MX6, not
the integrated PHY on i.MX7D. The OTG1 needs off-chip HSIC PHY or ULPI PHY
to work.This patch only supports OTG0 with UTMI PHY.
Signed-off-by: Ye Li
(cherry picked from commit 1ac22cabb96a14ac4ca58df60ae2025fb5e94db6)
(cherry picked from commit 53cfed1f967e44507a80a0b8c8113ae67188304b) -
support to read the flag status in driver to avoid the spi-nor framework
wait_for_ready hang issue.Signed-off-by: Han Xu
(cherry picked from commit 767faa948d2d140b6d56ee505f81f8f57c045a3d) -
There are two problems in enabling DDR mode in this new driver:
1. The TDH bits in FLSHCR register should be set to 1. Otherwise, the TX DDR delay logic
won't be enabled. Since u-boot driver does not have DDR commands in LUT. So this won't
cause explicit problem.
2. When doing read/write/readid/erase operations, the MCR register is overwritten, the bits
like DDR_EN are cleared during these operations. When we using DDR mode QSPI boot, the TDH bit
is set to 1 by ROM. if the DDR_EN is cleared, there is no clk2x output for TX data shift.
So these operations will fail.
The explicit problem is users may get "SF: unrecognized JEDEC id bytes: ff, ff, ff" error
after using DDR mode QSPI boot on 6UL/ULL EVK boards.Signed-off-by: Ye Li
(cherry picked from commit 16270556212e6c7422e87f69572c90f1afe6998b) -
The mx7ulp has small TX/RX FIFO (64Bytes) and AHB buffer size (128Bytes)
than other i.MX. Change some parameters for it.Also found when the DDR_EN bit is set, sometime the page programming will fail
during large data programming. The 64 bytes data is not programmed into flash.
But when DDR_EN is clear, there is no such issue. Suspect this is a IC issue.
We have disable the DDR_EN for mx7ulp.Signed-off-by: Ye Li
(cherry picked from commit 5a69ddb7e9886e082da42ddf673415702975ee60) -
Add MT35XU512ABA parameters to NOR flash parameters array. Since the
manufactory ID is changed to 0x2C, add it for micron and using it for
relevant settings.The MT35XU512ABA only supports 1 bit mode and 8 bits. It can't support
dual and quad. Because the 8 bits is not support by u-boot framework and
driver. We only use 1 bit mode for this flash.Signed-off-by: Ye Li
(cherry picked from commit 7595df64537e674df0a841563424b30b289d49fc) -
On mx7ulp B0, beside bank 0 and 1, the fuse bank 9, 10, 28 are changed to
Redundancy mode not ECC, so they can support to program different bits of
a word in multiple times.Signed-off-by: Ye Li
(cherry picked from commit af901cae281a617063559f60761ad4e912fccd5f) -
The i.MX6SL EVK needs this driver in android fastboot support. Add
this driver to u-boot.To use the driver, user must define:
CONFIG_MXC_KPD Enable the driver
CONFIG_MXC_KEYMAPPING Key mapping matrix
CONFIG_MXC_KPD_COLMAX The column size of key mapping matrix
CONFIG_MXC_KPD_ROWMAX The row size of the key mapping matrixSigned-off-by: Ye Li
(cherry picked from commit 5096e572667ff41217deb4ba9b1bd15e93fa6b59)
(cherry picked from commit e84160eaf5c057da45a227039c6f8a7911f43a82) -
The reset_sata should reset the sata device info and free the probe_ent
memory. Otherwise, it will cause memory leak if we init the sata again.Signed-off-by: Ye Li
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When sata stop is executed, the sata_curr_device is not reset to -1, so
any following sata commands will not initialize the sata again and cause
problem.Additional, in sata init implementation, the sata_curr_device should be updated,
otherwise sata will be initialized again when doing other sata commands like
read/write/info/part/device.Signed-off-by: Ye Li
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Currently the driver gets value from PSR register, but this register
is only for input mode. For output mode, it always return 0 not the
value we set for output.This patch changes to use DR register, which returns the DR value for
output mode, and PSR value for input mode.Signed-off-by: Ye Li
(cherry picked from commit 4afc3f90943c6b117f79b66d2cd04e64f437b0c2) -
For GPIO group which shared by multiple masters, it may set in RDC
to shared and semaphore required. Before access the GPIO register,
the GPIO driver must get the RDC semaphore, and release the semaphore
after the GPIO register access.When CONFIG_MXC_RDC is set, the features related to RDC semaphores
is enabled in mxc_gpio driver.Signed-off-by: Ye.Li
(cherry picked from commit 84d63e2e2ce12f714e88baad8b2325684614a7c1)
Signed-off-by: Peng FanConflicts:
drivers/gpio/mxc_gpio.c(cherry picked from commit c9943b9c8a78bb2c9886bfe582e82978387d8dee)
Signed-off-by: Peng Fan
(cherry picked from commit faf94726cac8316c4342e19936f1e03ef283ace3)
(cherry picked from commit 6c0474fe0e4fc543c62b22c05c2702a881f56418)
(cherry picked from commit 7cd5fec7ce6a9ecfdaa1a9c1aaaa0d0ac18a4f86) -
The pca953x_gpio driver uses default value of polarity inversion register.
For some devices like PCA9557 and MAX7310, their polarity inversion register
default value is 0xf0. So for high 4 ports, when reading their values,
the values are inverted as the actual level.This patch clears the polarity inversion register to 0 at init. So that the port read
and write values are aligned.Signed-off-by: Ye Li
Acked-by: Fugang Duan
Acked-by: Peng Fan
(cherry picked from commit cc4e6b3786671ec2ce2ea74dc6334f72587cc756) -
Should have "&" to access the register address, otherwise uboot will hang.
Signed-off-by: Ye Li
(cherry picked from commit 0b65071afaae9d6a49fb7dda2902f5c8bcd678c2)
(cherry picked from commit 712cbc4f23fa4276ae652b8767fd5a0646fab1da) -
This patch is a porting of
http://git.freescale.com/git/cgit.cgi/imx/linux-2.6-imx.git/commit/?h=imx_4.1.15_1.0.0_ga&id=e4dacc44d22e9474ec456cb330df525cd805ea38
"
i.MX6QP and i.MX7D BCH module integrated a new feature to detect the
bitflip number for erased NAND page. So for these two platform, set the
erase threshold to gf/2 and if bitflip detected, GPMI driver will
correct the data to all 0xFF.Also updated the imx6qp dts file to ditinguish the GPMI module for i.MX6Q
with the one for i.MX6QP.
"In this patch, i.MX6UL is added and threshold changed to use ecc_strength.
Signed-off-by: Peng Fan
(cherry picked from commit 489929be0221bb7d4c46bb5bc6083650b78f73e0)
Signed-off-by: Ye Li
(cherry picked from commit 37d7f9614aa357f270312d7ceaab0f7006dc5aea) -
This patch is porting from linux:
http://git.freescale.com/git/cgit.cgi/imx/linux-2.6-imx.git/commit/?h=imx_4.1.15_1.0.0_ga&id=3d42fcece496224fde59f9343763fb2dfc5b0768"
We may meet the bitflips in reading an erased page(contains all 0xFF),
this may causes the UBIFS corrupt, please see the log from Elie:-----------------------------------------------------------------
[ 3.831323] UBI warning: ubi_io_read: error -74 (ECC error) while reading 16384 bytes from PEB 443:245760, read only 16384 bytes, retry
[ 3.845026] UBI warning: ubi_io_read: error -74 (ECC error) while reading 16384 bytes from PEB 443:245760, read only 16384 bytes, retry
[ 3.858710] UBI warning: ubi_io_read: error -74 (ECC error) while reading 16384 bytes from PEB 443:245760, read only 16384 bytes, retry
[ 3.872408] UBI error: ubi_io_read: error -74 (ECC error) while reading 16384 bytes from PEB 443:245760, read 16384 bytes
...
[ 4.011529] UBIFS error (pid 36): ubifs_recover_leb: corrupt empty space LEB 27:237568, corruption starts at 9815
[ 4.021897] UBIFS error (pid 36): ubifs_scanned_corruption: corruption at LEB 27:247383
[ 4.030000] UBIFS error (pid 36): ubifs_scanned_corruption: first 6569 bytes from LEB 27:247383
-----------------------------------------------------------------This patch does a check for the uncorrectable failure in the following steps:
[0] set the threshold.
The threshold is set based on the truth:
"A single 0 bit will lead to gf_len(13 or 14) bits 0 after the BCH
do the ECC."For the sake of safe, we will set the threshold with half the gf_len, and
do not make it bigger the ECC strength.[1] count the bitflips of the current ECC chunk, assume it is N.
[2] if the (N
(cherry picked from commit ceb324a2914487aa517a6c70a06a20b5e3438fda)
(cherry picked from commit 026751697e41c7376414a8716cf0ea4bf998b85f) -
provide one config "CONFIG_NAND_MXS_BCH_LEGACY_GEO" to keep using legacy
bch geometry.NOTICE: the feature must be enabled/disabled in both u-boot and kernel.
Signed-off-by: Han Xu
(cherry picked from commit 0abc9c182c24f88522bd74fa1b53cd2fa3477184)
(cherry picked from commit 772af34b1216acc8e6a1a3faf43fef7c90b26a2f)
Signed-off-by: Ye Li
(cherry picked from commit 58794b3ebefea468bb1c57184b79df500f427927) -
The list_first_entry always assumes the list is not empty, it won't return NULL pointer when
the list is empty. So the "if (pdesc == NULL)" becomes a dead code. Fix the issue by calling
the list_empty before the list_first_entry.(Coverity CID 29934)
Signed-off-by: Ye.Li
(cherry picked from commit ff3923f294cc2e15f436d7520b4042736b1b48a6)
(cherry picked from commit 64c6a7b5d621080b8bd948c061a4f223a8c2d886) -
The cod change updated the NAND driver BCH ECC layout algorithm to
support large oob size NAND chips(oob > 1024 bytes).Current implementation requires each chunk size larger than oob size so
the bad block marker (BBM) can be guaranteed located in data chunk. The
ECC layout always using the unbalanced layout(Ecc for both meta and
Data0 chunk), but for the NAND chips with oob larger than 1k, the driver
cannot support because BCH doesn’t support GF 15 for 2K chunk.The change keeps the data chunk no larger than 1k and adjust the ECC
strength or ECC layout to locate the BBM in data chunk. General idea for
large oob NAND chips is1.Try all ECC strength from the minimum value required by NAND spec to
the maximum one that works, any ECC makes the BBM locate in data chunk
can be chosen.2.If none of them works, using separate ECC for meta, which will add one
extra ecc with the same ECC strength as other data chunks. This extra
ECC can guarantee BBM located in data chunk, of course, we need to check
if oob can afford it.Signed-off-by: Han Xu
(cherry picked from commit 78f620a6d6ab44bd34e42f00abe4673db099ca73)
(cherry picked from commit 242b2b889a9e18c587fafaa98cb9e9985b179df4) -
The wp-gpios property is used for gpio, if this is set, the WP pin is muxed
to gpio function, can't be used as internal WP checking.This patch changes to examine the "fsl,wp-controller" for using internal WP checking. And
wp-gpios for using gpio pin.Signed-off-by: Ye Li
(cherry picked from commit 733a7fde6fea35d6f2ea18c7759a06904b655e54) -
Since the probe function has changed to reset FEC controller prior than
setup PHY. If reset FEC controller timeout, the priv->phydev is not
initialized, so can't free it.Signed-off-by: Ye Li
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Add i.MX6UL/SX/SL/i.MX7D compatible.
Signed-off-by: Peng Fan
Acked-by: Joe Hershberger
