05 May, 2015
5 commits
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The SD clock could be generated by platform clock or peripheral
clock for some platforms. This patch adds peripheral clock
support for T1024/T1040/T2080. To enable it, define
CONFIG_FSL_ESDHC_USE_PERIPHERAL_CLK.Signed-off-by: Yangbo Lu
Cc: York Sun
Cc: Pantelis Antoniou
Reviewed-by: York Sun -
Add adapter card type identification support by reading
FPGA STAT_PRES1 register SDHC Card ID[0:2] bits. To use this function,
define CONFIG_FSL_ESDHC_ADAPTER_IDENT.Signed-off-by: Yangbo Lu
Cc: York Sun
Cc: Pantelis Antoniou
[York Sun: resolve conflicts in README.fsl-esdhc]
Reviewed-by: York Sun -
Freescale PCIe controllers v3.0 and later need to set bit
CFG_READY to allow all inbound configuration transactions
to be processed normally when in EP mode. However, bit
CFG_READY has been moved from PCIe configuration space to
CCSR PCIe configuration register comparing previous version.
The patch is to set this bit according to PCIe version.Signed-off-by: Ed Swarthout
Signed-off-by: Roy Zang
Signed-off-by: Minghuan Lian
Reviewed-by: York Sun -
T2080QDS PEX1/Slot#1 will down-train from x4 to x2,
with SRDS_PRTCL_S1 = 0x66 and SRDS_PRTCL_S2 = 0x15.
Soft reset PCIe can fix this issue.Signed-off-by: Zhao Qiang
Reviewed-by: York Sun -
Add a delay of 1 microsecond before issuing soft reset to the
controller to let ongoing ULPI transaction complete.
This prevents corruption of ULPI Function Control Register which
eventually prevents phy clock from entering to low power modeSigned-off-by: Nikhil Badola
Reviewed-by: York Sun
29 Apr, 2015
8 commits
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Remove the quirk SDHCI_QUIRK_NO_CD as it is not
required.Signed-off-by: Siva Durga Prasad Paladugu
Signed-off-by: Michal Simek -
On slow platforms not all baudrate setting is valid.
Check it directly in the driver and setup maximum possible
frequency.Signed-off-by: Michal Simek
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Most of the code is taken (and adapted) from Linux kernel driver.
Just add CONFIG_ZYNQ_GPIO to you config to enable it
Signed-off-by: Andrea Scian
Signed-off-by: Michal Simek -
These functions now rely on uclass_find_first/next_device() and assume that
they will either return failure (-ve error code) or a device. In fact,
coming to the end of a list is not considered failure and they return 0
in that case.The logic to deal with this was replaced in commit acb9ca2a with just using
uclass_get_device_tail(). Add back the missing logic. This bug was
caught by unit tests but since they were broken for other reasons at the
time, this was not noticed.Signed-off-by: Simon Glass
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This was accidentally added by commit dd0b0122bacc
"serial: ns16550: Add an option to specify the debug UART register shift".
Remove it.Signed-off-by: Axel Lin
Acked-by: Simon Glass -
Trivial bug fix for commit 5a87c4174d18 (dm: core: Drop device
removal error path when not supported).Signed-off-by: Masahiro Yamada
Acked-by: Simon Glass
28 Apr, 2015
4 commits
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Upto now flash sector_size is assigned from params which isn't
necessarily a sector size from vendor, so based on the SECT_*
flags from flash_params the erase_size will compute and it will
become the sector_size finally.Bug report (from Bin Meng):
=> sf probe
SF: Detected SST25VF016B with page size 256 Bytes, erase size 4 KiB,
total 2 MiB, mapped at ffe00000=> sf erase 0 +100
SF: 65536 bytes @ 0x0 Erased: OKSigned-off-by: Jagannadha Sutradharudu Teki
Reported-by: Bin Meng
Tested-by: Bin Meng -
With SPI flash moving to driver model, commit fbb0991 "dm: Convert
spi_flash_probe() and 'sf probe' to use driver model" ignored the
SST flash-specific write op (byte program & word program), which
actually broke the SST flash from wroking.This commit makes SST flash work again under driver model, by adding
SST flash-specific handling in the spi_flash_std_write().Signed-off-by: Bin Meng
Reviewed-by: Jagannadha Sutradharudu Teki -
Add a new member 'flags' in struct spi_flash to store the flash flags
during spi_flash_validate_params().Signed-off-by: Bin Meng
Reviewed-by: Jagannadha Sutradharudu Teki
27 Apr, 2015
1 commit
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The timeout value is never reset during the transfer. This means that when
transferring more data we eventually trigger the timeout.This was reported on the mailing list:
"Spansion SPI flash read timeout with AM335x"Signed-off-by: David Dueck
CC: Tom Rini
CC: Stefan Roese
CC: Andy Pont
Tested-by: David Dueck
Reviewed-by: Jagannadha Sutradharudu Teki
25 Apr, 2015
1 commit
24 Apr, 2015
8 commits
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This patch adds esdhc support for ls2085a.
Signed-off-by: Yangbo Lu
Signed-off-by: York Sun -
This adds NAND boot support for LS2085AQDS, using SPL framework.
Details of forming NAND image can be found in README.Signed-off-by: Scott Wood
[York Sun: Remove +S from defconfig after commit 252ed872]
Signed-off-by: York Sun -
IFC has two register pages.Till IFC version 1.4 each
register page is 4KB each.But IFC ver 2.0 register page
size is 64KB each.IFC regiters structure is break into
two viz FCM and RUNTIME.FCM(Flash control machine) registers
are defined in PAGE0 and controls IFC generic functionality.
RUNTIME registers are defined in PAGE1 and controls NAND and
GPCM funcinality.FCM and RUNTIME structures defination is common for IFC
version 1.4 and 2.0.Signed-off-by: Jaiprakash Singh
Signed-off-by: York Sun -
Add support of ethernet:
- eth.c: mapping lane to slot for (0x2A, 0x07)
- ls2085a.c: To enable/disable dpmac and get link typeSigned-off-by: Prabhakar Kushwaha
Signed-off-by: York Sun -
This driver adds support for the USB peripheral on Freescale Vybrid
SoC's.Signed-off-by: Sanchayan Maity
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The Marvell GPIO driver can be used on Marvell platforms other than
Sheeva, so remove the ifdef to enable it for others.Signed-off-by: Rob Herring
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1. The bits 11..10 for mfp driver strength is only valid for
aspen and old xscale family, for newer Marvell chip, this range
has been moved to 12..11.
2. add sleep bit supportSigned-off-by: Xiang Wang
[robh: rebase to current mainline]
Signed-off-by: Rob Herring
23 Apr, 2015
13 commits
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Wire rate IO Processor (WRIOP) provide support of receive and transmit
ethernet frames from the ethernet MAC. Here Each WRIOP block supports
upto 64 DPMACs.Create a house keeping data structure to support upto 16 DPMACs and
store external phy related information.Signed-off-by: Prabhakar Kushwaha
Signed-off-by: York Sun -
The memac for PHY management on little endian SoCs is similar on big
endian SoCs, so we modify the driver by using I/O accessor function to
handle the endianness, so the driver can be reused on little endian
SoCs, we introduce CONFIG_SYS_MEMAC_LITTLE_ENDIAN for little endian
SoCs, if the CONFIG_SYS_MEMAC_LITTLE_ENDIAN is defined, the I/O access
is little endian, if not, the I/O access is big endian. Move fsl_memac.h
out of powerpc include.Signed-off-by: Shaohui Xie
Signed-off-by: York Sun -
Changed MC firmware loading to comply with the new MC boot architecture.
Flush D-cache hierarchy after loading MC images. Add environment
variables "mcboottimeout" for MC boot timeout in milliseconds,
"mcmemsize" for MC DRAM block size. Check MC boot status before calling
flib functions.Signed-off-by: J. German Rivera
Signed-off-by: York Sun -
Fix comilation warning which is emitted when
firmware address is more than 32 bit.Signed-off-by: pankaj chauhan
Signed-off-by: York Sun -
Fix flush_dcache_range() input parameter to use start and end addresses.
Change ethernet interface name to DPNI. Update entry criteria for
ldpaa_eth_stop. Ethernet stack first stop the device before performing
next operation. At the time of Ethernet driver registration,
net_dev->state is set as ETH_STATE_INIT So take care net_dev->state as
ETH_STATE_INIT in ldpaa_eth_stop.Undef CONFIG_PHYLIB temorarily because ldpaa_eth driver currently does
not support PHYLIB.Instead of clearing pull descriptor one time, clear it before issuing any
volatile dequeue command.Volatile command does not return frame immidiately, wait till a frame
is available in DQRR. This frame can be valid or expired.Flush buffer before releasing to BMan ensure the core does not have any
cachelines that the WRIOP will DMA to.Signed-off-by: Prabhakar Kushwaha
Signed-off-by: pankaj chauhan
Signed-off-by: Roy Pledge
Signed-off-by: York Sun -
The patch removes unnecessary whitespace to fix checkpatch's
warning: unnecessary whitespace before a quoted newlineSigned-off-by: Minghuan Lian
Acked-by: Joe Hershberger
Reviewed-by: York Sun -
This erratum only applies to general purpose DDR controllers in LS2.
It shouldn't be applied to DP-DDR controller. Check DDRC versoin number
before applying workaround.Signed-off-by: York Sun
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Add built-in memory test to catch errors after DDR is initialized, before
any other transactions. To enable this test, define CONFIG_FSL_DDR_BIST.
An environmental variable "ddr_bist" is checked before starting test.
It takes a while (several seconds) depending on system memory size.Signed-off-by: York Sun
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CS0 was not allowed to be empty by u-boot driver in the past to simplify
the driver. This may be inconvenient for some debugging. This patch lifts
the restrictions. Controller interleaving still requires CS0 populated.Signed-off-by: York Sun
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Add/update registers for DDR4, including DQ mappings. Allow raw timing
method used for all controllers. Update mode_9 register to 0x500 for
improved stability. Check DDR controller version number individually
in case a SoC has multiple DDR controllers of different versions.
Increase read-write turnaround for DDR4 high speeds.Signed-off-by: York Sun
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Some SoCs have more than two I2C busses. Instead of adding ifdef
to the driver, macros are put into board header file where
CONFIG_SYS_I2C_MXC is defined.Signed-off-by: York Sun
CC: Heiko Schocher -
IFC 2.0 doubled the SRAM size, which means double the number of
ECCSTAT registers. Fix the resulting array overflow.Signed-off-by: Scott Wood
Reviewed-by: York Sun -
For fsl-lsch3, IFC is binded with address within 32-bit at fist.
After u-boot relocates to DDR, CS1, CS3 can be binded to higher
address to support large space.Signed-off-by: Prabhakar Kushwaha
Signed-off-by: York Sun
