18 Mar, 2019
1 commit
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Update the lpddr4 timing config to align with the ddr tool
Signed-off-by: Jacky Bai
Reviewed-by: Ye Li
(cherry picked from commit a1433dec3a03a6c944b61600e7b317e2a83f2981)
26 Feb, 2019
3 commits
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When flexspi is assigned to M4 for XIP, its power up/down will fail.
This is expected so don't need to give warning.Signed-off-by: Ye Li
(cherry picked from commit 0803b4a9d4074a5bb101d194633cbdd7510a1e9a) -
The CONFIG_QSPI_BOOT has been removed from SPL flexspi build, because
we have to change the u-boot ENV to SD/MMC, and this configuration will
set relevant configurations.But we don't clean up CONFIG_QSPI_BOOT for SPL completely, SPL still has
some places using it and cause problem to flexspi boot.
Using CONFIG_SPL_SPI_SUPPORT to replace the CONFIG_QSPI_BOOT.Signed-off-by: Ye Li
(cherry picked from commit 0491bd4ba21ad620b4c514323a7d6b8a9e10325c) -
Update the ddr training code to work with the atf 2.0.
Test: Build and boot on imx8mq aiy 3G board.
Change-Id: I8546c34cfa4aeeed819f7797f8362676e420b41f
Signed-off-by: Ji Luo
25 Feb, 2019
1 commit
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When M4 is booted by ROM, we have to enable RPMSG in kernel, so need
to select the -rpmsg.dtb. If M4 is not enabled, use default kernel dtb.Signed-off-by: Ye Li
Reviewed-by: Peng Fan
(cherry picked from commit 8a57be45e18295ce1b19799723775cf5b205281d)
12 Feb, 2019
1 commit
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Since we have asked SCFW to do this job to avoid issues in partition
reboot, remove relevant codes.Signed-off-by: Ye Li
(cherry picked from commit 8128566e843d76720cdc5c3e075fa303e401132f)
11 Feb, 2019
1 commit
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According to latest datasheet IMX8MMCEC_Rev_0, the typical voltage
of VDD_DRAM for 1.5GHz DDR clock is 0.95v. Because BD71847MWV PMIC
does not support 0.95v output. We change the voltage to 0.975v as
the note in datasheet mentioned it is acceptable and supported.Signed-off-by: Ye Li
Reviewed-by: Bai Ping
25 Jan, 2019
2 commits
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SCFW has taken to reset the base board by deasserting BB_PER_RST_B(SCU_GPIO0_01) on
imx8QM MEK board, and has removed the SC_R_BOARD_R1 functionality.
So We don't need to explicitly use SC_R_BOARD_R1, delete the codes from u-boot.Signed-off-by: Ye Li
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There are two new validation boards: LPDDR4 board (30123) and DDR3L board (30010)
for imx8x family 17x17 chips. These two boards have same design except the DDR.
Since SCFW is resposible for DDR initialization, U-boot could use one build to
cover two boards.
The 8DX 17x17 DDR3L ARM2 has been added into u-boot before, so we rename the config
CONFIG_TARGET_IMX8DX_DDR3_ARM2 to CONFIG_TARGET_IMX8X_17X17_VAL to cover DDR3L and
LPDDR4.Considering 8DX and 8QXP 17x17 may solder to the boards, we create two defconfig:
one for DX and another for 8qxp to share with the CONFIG_TARGET_IMX8X_17X17_VAL
but with different FDTs.Signed-off-by: Ye Li
21 Jan, 2019
2 commits
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According to the latest datasheet, software is expected to program
the VDD_SOC voltage to the typical value 0.85V prior to the first
DRAM memory access. At default the VDD_SOC is 0.8V from PMIC BUCK1,
so we have to change it to 0.85V in SPL.Signed-off-by: Ye Li
Tested-by: Anson Huang -
Enable the new mipi panel driver and add parameters to board codes.
We enable the RM68200_WXGA as default panel, users can set "panel"
environment variable to switch to different panel.Signed-off-by: Ye Li
Reviewed-by: Fancy Fang
09 Jan, 2019
2 commits
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Enable the SPL SDP driver and USB driver in MEK board codes and defconfigs.
Because the USB driver needs larger malloc pool, increase the malloc size
and disable simple mallocSigned-off-by: Ye Li
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The SPL won't use host mode, and the tcpc is default set as device mode.
So we don't need to access tcpc in SPL.Signed-off-by: Ye Li
26 Dec, 2018
1 commit
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Since the gpio non-dm driver maps to wrong GPIO register, the SPL
also powers up wrong GPIO resources.Signed-off-by: Ye Li
Acked-by: Peng Fan
20 Dec, 2018
2 commits
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The HAB code can not set Field Return and SRK Revoke sticky bits in case
OCOTP CTRL clock is gated out.In case we disable OCOTP CTRL clock in DCD and plugin those features may
not operate as expected.Keep OCOTP CTRL clock enabled in DCD and plugin so HAB can propely lock
those features, users should use the CSF Unlock command to prevent those
features from being locked.Signed-off-by: Breno Lima
Reviewed-by: Ye Li -
The HAB code can not set Field Return and SRK Revoke sticky bits in case
OCOTP CTRL clock is gated out.In case we disable OCOTP CTRL clock in DCD and plugin those features may
not operate as expected.Keep OCOTP CTRL clock enabled in DCD and plugin so HAB can propely lock
those features, users should use the CSF Unlock command to prevent those
features from being locked.Signed-off-by: Breno Lima
18 Dec, 2018
1 commit
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Keep high speed for SPL, but for normal uboot, enable super speed.
Reviewed-by: Ye Li
Reviewed-by: Peter Chen
Tested-by: faqiang.zhu
Signed-off-by: Li Jun
12 Dec, 2018
2 commits
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Write magic number in board early init, and clear magic when booting
Linux.This is to let XEN know the current EL1 code is U-Boot or Linux
when reset/reboot. This is just a workaround because CM41 could not
communicate with XEN now, even XEN knows that EL1 is reseting/rebooting.Signed-off-by: Peng Fan
Reviewed-by: Flynn xu -
To support partition reboot, the u-boot has to enable clocks by LPCG.
The LPCG will reset to default value only when the subsystem is totally
power off and reset. However, the resources in one subsystem may belong
to different partitions, so the partition reboot may not reboot the entire
subsystem.
Powers, clocks/lpcg, GPR, IP may not reset depends on various cases and
HW design. Thus, AP software has to ensure everything is reset by SW
itself to support such above cases.Signed-off-by: Ye Li
26 Nov, 2018
1 commit
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Add support for new target imx8mq_aiy.
Test: build and boot ok on imx8mq_aiy.
Change-Id: I7bb8b66e5235a7122073dcfb4cdc7f165036b9a6
Signed-off-by: Ji Luo
20 Nov, 2018
1 commit
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Update the ddrc Qos setting for B1 to align with B0'ssetting.
Correct the initial clock for dram_pll. This setting will be
overwrite before ddr phy training. Although there is no impact
on the dram init, we still need to correct it to eliminate
confusion.Signed-off-by: Bai Ping
Reviewed-by: Ye Li
Tested-by: Robby Cai
12 Nov, 2018
6 commits
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- temp fix for boot hangup with camera
This reverts commit a8109598e7dca72d415ad5d26ac5868b88da9dfc.
Bug: 115532706
Test: test boot up
Change-Id: I7bb1bc14eb81ae0965fc03abdf5cb65444720d13 -
Add fastboot commands "fastboot oem at-get-vboot-unlock-challenge"
and "fastboot oem at-unlock-vboot" to support the authenticated
unlock feature for Android Things devices. Use software random
numbers generator to generate the 16 bytes random challenge, it
should be replaced with hardware encrypted random generator when
the TEE part is ready.Test: Generate unlock challenge by:
./avbtool make_atx_unlock_credential
--output=atx_unlock_credential.bin
--intermediate_key_certificate=atx_pik_certificate.bin
--unlock_key_certificate=atx_puk_certificate.bin
--challenge=my_generated_challenge.bin
--unlock_key=testkey_atx_puk.pem
validated the unlock credential successfully on imx7d_pico
and AIY.Change-Id: I4b8cee87c9e96924169479b65020a081136681f6
Signed-off-by: Ji Luo -
Trusty image should be loaded to different address for AIY 1G/3G ddr
board which have different ddr size. Use board id to distinguish
different baseboard, load trusty image to 0x7e00_0000 for AIY 1G ddr
board and 0xfe00_0000 for AIY 3G ddr board.Test: build and boot Trusty ok for AIY 1G/3G ddr board.
Change-Id: I62d8a19b13fe19f38075512a6faa4bbb36f74791
Signed-off-by: Ji Luo -
Because sysdeps.h in trusty include stdint.h, so we need to define
USE_STDINT.Test: Local build test and flash on imx7d. Verify provision som
key and product key succeed.
Bug: None
Change-Id: I08db7c10dd4453a87f15ff4432335fe4c41f9c5f -
for 1GB ram: cma=296M galcore.contiguousSize=8388608
for 3GB ram: cma=384M
Test: Boot successfully on AIY-1G & AIY-3GChange-Id: If082d5b751b5a5e06efe301c0b8e49ec4ac3dfb7
Signed-off-by: faqiang.zhu
Reviewed-on: http://androidsource.ap.freescale.net/project/5262
Reviewed-by: Wang Haoran
Signed-off-by: faqiang.zhu -
Set BUCK2 output for VDD_ARM to 0.85v
Set BUCK3 output for VDD_GPU off
Set BUCK4 output for VDD_VPU offChange-Id: I26b47b72ae6b8e714d12345b20324490f0947f56
Signed-off-by: faqiang.zhu
Reviewed-on: http://androidsource.ap.freescale.net/project/5177
Reviewed-by: zhang bo
07 Nov, 2018
1 commit
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The power domain driver is not ready when running board_early_init_f,
but we call it imx8qxp_gpmi_nand_initialize. so this cause u-boot reset
in early stage.Signed-off-by: Ye Li
Tested-by: Han Xu
03 Nov, 2018
7 commits
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Refact the i.MX8MQ dram init flow to reuse the common dram
driver used by i.MX8MM.Signed-off-by: Bai Ping
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Change the dram_pll_init function API to make it same
as i.MX8MM, so the dram init flow can use call the same
API for these two different SOC.Signed-off-by: Bai Ping
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Because u-boot USB gadget only can support one driver, so if we enable
ci_udc driver, the cdns3 gadget driver must be disabled. This cause build
error because we don't wrap the cdns gadget functions with its configuration.Fix the issue by adding CONFIG_USB_CDNS3_GADGET before cdns3 gadget function.
Signed-off-by: Ye Li
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Because the iMX8MQ DDR4 ARM2 has 4GB DDR. To fit new MMU settings, we split
it to two banks. The first bank has 3GB DDR, reach to 4GB memory map.
The second bank has 1GB DDR, is beyond 4GB memory map.Notice: there is no OPTEE for ARM2 board. The trust zone setting in OPTEE
for iMX8MQ EVK is not match with DDR size on ARM2 board. So ARM2 Only can
work without OPTEE.Signed-off-by: Ye Li
Reviewed-by: Peng Fan -
iMX8MM DDR3L validation board uses FPGA to link with SPI NOR flash
on ECSPI1 port. Update the codes and configurations to enable the
ECSPI1 to access SPI NOR in u-boot.Signed-off-by: Ye Li
Reviewed-by: Peng Fan -
Add implementation necessary for supporting SPL on QXP
ARM2 board with dynamic offset detection from container header.Signed-off-by: Teo Hall
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The iMX7ULP B0 chip has added more pins for muxing USB ID. The A3 board
follows it to exploit PTC13 for USB ID, so we don't need to use GPIO
any longer. The USB driver can recognize the USB mode from USB PHY.After this change, old boards with design using GPIO for USB mode won't
be supported.Signed-off-by: Ye Li
27 Oct, 2018
1 commit
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enable CE_1 IOMUX setting for NAND on i.MX8MM EVK
Signed-off-by: Han Xu
25 Oct, 2018
2 commits
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Update the RFSHCTL3 config for DDR4.
Signed-off-by: Bai Ping
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Add DDR3 init codes, board codes, defconfig and DTS into u-boot.
Basic modules are ready: SD, UART, I2C, USB host and NAND.There is a FPGA on this board. It controls WDOG_B, and ENET PHY RESET.
So reset and ethernet won't work at default.Signed-off-by: Ye Li
Acked-by: Peng Fan
16 Oct, 2018
2 commits
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Add support for FIT image loading of ATF and uboot proper for iMX8QXP mek.
Signed-off-by: Abel Vesa
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Add support for FIT image loading of ATF and uboot proper for iMX8QM mek.
Signed-off-by: Abel Vesa