Eric Lee / smarc-uboot

25 Feb, 2014

1 commit

04 Feb, 2014

5 commits

25 Jan, 2014

7 commits

23 Jan, 2014

1 commit

  • f28bea000   eSDHC: Calculate envaddr accroding to the address format ... Browse Code »

    On BSC9131, BSC9132, P1010 : For High Capacity SD Cards (> 2 GBytes), the
    32-bit source address specifies the memory address in block address
    format. Block length is fixed to 512 bytes as per the SD High Capacity
    specification. So we need to convert the block address format
    to byte address format to calculate the envaddr.

    If there is no enough space for environment variables or envaddr
    is larger than 4GiB, we relocate the envaddr to 0x400. The address
    relocated is in the front of the first partition that is assigned
    for sdboot only.

    Signed-off-by: Haijun Zhang
    Acked-by: Pantelis Antoniou
    Reviewed-by: York Sun

    Haijun.Zhang
     

22 Jan, 2014

4 commits

03 Jan, 2014

2 commits

  • 2ffa96d81   powerpc/t208x: fix macro CONFIG_SYS_FSL_NUM_USB_CTRLS ... Browse Code »

    CONFIG_SYS_FSL_NUM_USB_CTRLS is no longer used,
    update it to new CONFIG_USB_MAX_CONTROLLER_COUNT.

    Signed-off-by: Shengzhou Liu

    Shengzhou Liu
     
  • b135991a3   powerpc/mpc85xx: Add support for single source clocking ... Browse Code »

    Single-source clocking is new feature introduced in T1040.
    In this mode, a single differential clock is supplied to the
    DIFF_SYSCLK_P/N inputs to the processor, which in turn is
    used to supply clocks to the sysclock, ddrclock and usbclock.

    So, both ddrclock and syclock are driven by same differential
    sysclock in single-source clocking mode whereas in normal clocking
    mode, generally separate DDRCLK and SYSCLK pins provides
    reference clock for sysclock and ddrclock

    DDR_REFCLK_SEL rcw bit is used to determine DDR clock source
    -If DDR_REFCLK_SEL rcw bit is 0, then DDR PLLs are driven in
    normal clocking mode by DDR_Reference clock

    -If DDR_REFCLK_SEL rcw bit is 1, then DDR PLLs are driven in
    single source clocking mode by DIFF_SYSCLK

    Add code to determine ddrclock based on DDR_REFCLK_SEL rcw bit.

    Signed-off-by: Poonam Aggrwal
    Signed-off-by: Priyanka Jain

    Priyanka Jain
     

16 Dec, 2013

2 commits

  • e8a8b8246   Makefile: Select objects by CONFIG_ rather than $(ARCH) or $(CPU) ... Browse Code »

    Convert like follows:

    CPU mpc83xx -> CONFIG_MPC83xx
    CPU mpc85xx -> CONFIG_MPC85xx
    CPU mpc86xx -> CONFIG_MPC86xx
    CPU mpc5xxx -> CONFIG_MPC5xxx
    CPU mpc8xx -> CONFIG_8xx
    CPU mpc8260 -> CONFIG_8260
    CPU ppc4xx -> CONFIG_4xx
    CPU x86 -> CONFIG_X86
    ARCH x86 -> CONFIG_X86
    ARCH powerpc -> CONFIG_PPC

    Signed-off-by: Masahiro Yamada

    Masahiro Yamada
     
  • 871a57bb8   common/cmd_bootm: extend do_bootm_vxworks to support the new VxWorks boot interface. ... Browse Code »

    The next version VxWorks adopts device tree (for PowerPC and ARM) as its hardware
    description mechanism. For PowerPC, the boot interface conforms to
    the ePAPR standard, which is:

    void (*kernel_entry)(ulong fdt_addr,
    ulong r4 /* 0 */,
    ulong r5 /* 0 */,
    ulong r6 /* EPAPR_MAGIC */, ulong r7 /* IMA size */,
    ulong r8 /* 0 */, ulong r9 /* 0 */)

    For ARM, the boot interface is:

    void (*kernel_entry)(void *fdt_addr)

    Signed-off-by: Miao Yan
    [trini: Fix build error when !CONFIG_OF_FDT is set, typo on PowerPC,
    missing extern ft_fixup_num_cores]
    Signed-off-by: Tom Rini

    Miao Yan
     

13 Dec, 2013

1 commit

12 Dec, 2013

2 commits

05 Dec, 2013

3 commits

  • 1df99080c   powerpc/mpc8349: Use generic mpc85xx DDR driver ... Browse Code »

    MPC8349 has been using mpc85xx DDR driver through a symbolic link to
    mpc85xx_ddr_gen2.c. After consolidating the drivers to a single set
    under driver/ddr/fsl/, the link is replaced by referring driver
    directly. We now can simply enable the macro and use the driver.
    Other mpc83xx SoCs still use their own driver.

    Signed-off-by: York Sun

    York Sun
     
  • e88f421e7   T4240: Address T4240/T4160 Rev2.0 DDR clock change ... Browse Code »

    MEM_PLL_RAT on T4240/T4160 Rev2.0 uses a value which is half of Rev1.0.
    It's 12 in Rev1.0, for Rev2.0 it uses 6.

    Signed-off-by: Roy Zang
    Signed-off-by: Shaohui Xie
    Acked-by: York Sun

    Zang Roy-R61911
     
  • 24936ed1c   powerpc/corenet: CPC1 speculation disable ... Browse Code »

    In PBL RAMBOOT(SPI/SD/NAND boot) mode, CPC1 used as SRAM, should disable
    CPC1 speculation and keep it till relocation. Otherwise, speculation
    transactions will go to DDR controller, it will cause problem.

    Signed-off-by: Dave Liu
    Signed-off-by: Shaohui Xie
    Acked-by: York Sun

    Dave Liu
     

26 Nov, 2013

6 commits

  • 629d6b32d   powerpc/mpc85xx: Add T2080/T2081 SoC support ... Browse Code »

    Add support for Freescale T2080/T2081 SoC.

    T2080 includes the following functions and features:
    - Four dual-threads 64-bit Power architecture e6500 cores, up to 1.8GHz
    - 2MB L2 cache and 512KB CoreNet platform cache (CPC)
    - Hierarchical interconnect fabric
    - One 32-/64-bit DDR3/3L SDRAM memory controllers with ECC and interleaving
    - Data Path Acceleration Architecture (DPAA) incorporating acceleration
    - 16 SerDes lanes up to 10.3125 GHz
    - 8 mEMACs for network interfaces (four 1Gbps MACs and four 10Gbps/1Gbps MACs)
    - High-speed peripheral interfaces
    - Four PCI Express controllers (two PCIe 2.0 and two PCIe 3.0 with SR-IOV)
    - Two Serial RapidIO 2.0 controllers/ports running at up to 5 GHz
    - Additional peripheral interfaces
    - Two serial ATA (SATA 2.0) controllers
    - Two high-speed USB 2.0 controllers with integrated PHY
    - Enhanced secure digital host controller (SD/SDHC/SDXC/eMMC)
    - Enhanced serial peripheral interface (eSPI)
    - Four I2C controllers
    - Four 2-pin UARTs or two 4-pin UARTs
    - Integrated Flash Controller supporting NAND and NOR flash
    - Three eight-channel DMA engines
    - Support for hardware virtualization and partitioning enforcement
    - QorIQ Platform's Trust Architecture 2.0

    Differences between T2080 and T2081:
    Feature T2080 T2081
    1G Ethernet numbers: 8 6
    10G Ethernet numbers: 4 2
    SerDes lanes: 16 8
    Serial RapidIO,RMan: 2 no
    SATA Controller: 2 no
    Aurora: yes no
    SoC Package: 896-pins 780-pins

    Signed-off-by: Shengzhou Liu
    Acked-by: York Sun

    Shengzhou Liu
     
  • 82a55c1ef   net/fman: Add support for 10GEC3 and 10GEC4 ... Browse Code »

    There are more than two 10GEC in single FMAN in some SoCs(e.g. T2080).
    This patch adds support for 10GEC3 and 10GEC4.

    Signed-off-by: Shengzhou Liu

    Shengzhou Liu
     
  • 0b66513b2   Driver/IFC: Move Freescale IFC driver to a common driver ... Browse Code »

    Freescale IFC controller has been used for mpc8xxx. It will be used
    for ARM-based SoC as well. This patch moves the driver to driver/misc
    and fix the header file includes.

    Signed-off-by: York Sun

    York Sun
     
  • 9a17eb5b7   Driver/DDR: combine ccsr_ddr for 83xx, 85xx and 86xx ... Browse Code »

    Fix ccsr_ddr structure to avoid using typedef. Combine DDR2 and DDR3
    structure for 83xx, 85xx and 86xx.

    Signed-off-by: York Sun

    York Sun
     
  • 5614e71b4   Driver/DDR: Moving Freescale DDR driver to a common driver ... Browse Code »

    Freescale DDR driver has been used for mpc83xx, mpc85xx, mpc86xx SoCs.
    The similar DDR controllers will be used for ARM-based SoCs.

    Signed-off-by: York Sun

    York Sun
     
  • f40fcfd91   mpc85xx: Fix the offset of register address error ... Browse Code »

    The offset of register address within GPIO module is just
    CONFIG_SYS_MPC85xx_GPIO_ADDR. So, fix it. The following platforms
    are confirmed: MPC8572, P1023, P1020, P1022, P2020, P4080,
    P5020, P5040, T4240, B4860.

    Signed-off-by: Tang Yuantian

    Tang Yuantian
     

18 Nov, 2013

5 commits

14 Nov, 2013

1 commit

  • 51abee64e   powerpc/85xx: fix broken cpu "clock-frequency" property ... Browse Code »

    When indexing freqProcessor[] we use the first
    value in the cpu's "reg" property, which on
    new e6500 cores IDs the threads.
    But freqProcessor[] should be indexed with a
    core index so, when fixing "the clock-frequency"
    cpu node property, access the freqProcessor[]
    with the core index derived from the "reg' property.
    If we don't do this, last half of the "cpu" nodes
    will have broken "clock-frequency" values.

    Signed-off-by: Laurentiu Tudor
    Cc: York Sun

    Laurentiu TUDOR