25 Feb, 2014
2 commits
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In the previous patches, we introduced the SPL/TPL fraamework.
For SD/SPI flash booting way, we introduce the SPL to enable a loader stub. The
SPL was loaded by the code from the internal on-chip ROM. The SPL initializes
the DDR according to the SPD and loads the final uboot image into DDR, then
jump to the DDR to begin execution.For NAND booting way, the nand SPL has size limitation on some board(e.g.
P1010RDB), it can not be more than 8KB, we can call it "minimal SPL", So the
dynamic DDR driver doesn't fit into this minimum SPL. We added the TPL that is
loaded by the the minimal SPL. The TPL initializes the DDR according to the SPD
and loads the final uboot image into DDR,then jump to the DDR to begin execution.This patch enabled SPL/TPL for P1010RDB to support starting from NAND/SD/SPI
flash with SPL framework and initializing the DDR according to SPD in the SPL/TPL.
Because the minimal SPL load the TPL to L2 SRAM and the jump to the L2 SRAM to
execute, so the section .resetvec is no longer needed.Signed-off-by: Ying Zhang
Reviewed-by: York Sun -
T2081 QDS is a high-performance computing evaluation, development and
test platform supporting the T2081 QorIQ Power Architecture processor.T2081QDS board Overview
-----------------------
- T2081 SoC integrating four 64-bit dual-threads e6500 cores up to 1.8GHz
- 2MB shared L2 and 512KB L3 CoreNet platform cache (CPC)
- CoreNet fabric supporting coherent and noncoherent transactions with
prioritization and bandwidth allocation
- 32-/64-bit DDR3/DDR3LP SDRAM memory controller with ECC and interleaving
- Ethernet interfaces:
- Two on-board 10M/100M/1G bps RGMII ports
- Two 10Gbps XFI with on-board SFP+ cage
- 1Gbps/2.5Gbps SGMII Riser card
- 10Gbps XAUI Riser card
- Accelerator:
- DPAA components consist of FMan, BMan, QMan, PME, DCE and SEC
- SerDes:
- 8 lanes up to 10.3125GHz
- Supports SGMII, HiGig, XFI, XAUI and Aurora debug,
- IFC:
- 512MB NOR Flash, 2GB NAND Flash, PromJet debug port and Qixis FPGA
- eSPI:
- Three SPI flash (16MB N25Q128A + 16MB EN25S64 + 512KB SST25WF040)
- USB:
- Two USB2.0 ports with internal PHY (one Type-A + one micro Type mini-AB)
- PCIe:
- Four PCI Express controllers (two PCIe 2.0 and two PCIe 3.0 with SR-IOV)
- eSDHC:
- Supports various SD/SDHC/SDXC/eMMC devices with adapter cards and
voltage translators
- I2C:
- Four I2C controllers.
- UART:
- Dual 4-pins UART serial portsSigned-off-by: Shengzhou Liu
Reviewed-by: York Sun
07 Feb, 2014
4 commits
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With this change driver will benefit from existing phylib and thus
custom phy functionality implemented in the driver will go away:
* Instantiation of the driver is now much shorter - 2 parameters
instead of 4.
* Simplified phy management/functoinality in driver is replaced with
rich functionality of phylib.
* Support of custom phy initialization is now done with existing
"board_phy_config".Note that after this change some previously used config options
(driver-specific PHY configuration) will be obsolete and they are simply
substituted with similar options of phylib.For example:
* CONFIG_DW_AUTONEG - no need in this one. Autonegotiation is enabled
by default.
* CONFIG_DW_SEARCH_PHY - if one wants to specify attached phy
explicitly CONFIG_PHY_ADDR board config option has to be used, otherwise
automatically the first discovered on MDIO bus phy will be usedI believe there's no need now in "doc/README.designware_eth" because
user only needs to instantiate the driver with "designware_initialize"
whose prototype exists in "include/netdev.h".Cc: Joe Hershberger
Cc: Vipin Kumar
Cc: Stefan Roese
Cc: Mischa Jonker
Cc: Shiraz Hashim
Cc: Albert ARIBAUD
Cc: Amit Virdi
Cc: Sonic Zhang
Signed-off-by: Alexey Brodkin -
AXS101 is a new generation of devlopment boards from Synopsys that houses
ASIC with ARC700 and lots of DesignWare peripherals:* DW APB UART
* DW Mobile Storage (MMC/SD)
* DW I2C
* DW GMACSigned-off-by: Alexey Brodkin
Cc: Vineet Gupta
Cc: Francois Bedard
Cc: Wolfgang Denk
Cc: Heiko Schocher -
Arcangel4 is a FPGA-based development board that is used for prototyping and
verificationof of both ARC hardware (CPUs) and software running upon CPU.This board avaialble in 2 flavours:
* Little-endian (arcangel4)
* Big-endian (arcangel4-be)Signed-off-by: Alexey Brodkin
Cc: Vineet Gupta
Cc: Francois Bedard
Cc: Wolfgang Denk
Cc: Heiko Schocher
06 Feb, 2014
2 commits
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Just extend tables with this new device.
Signed-off-by: Michal Simek
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The mv_udc is not marvell-specific anymore. The mv_udc is used to drive
generic ChipIdea CI13xxx series OTG cores, so rename the driver to ci_udc
instead.Signed-off-by: Marek Vasut
Cc: Eric Nelson
Cc: Stefano Babic
04 Feb, 2014
9 commits
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The PEXHC PCIe configuration mechanism ensures that the FPGA get
configured at power-up. Since all the PCIe devices should be configured
when the kernel start, u-boot has to take care that the FPGA gets
configured also in other reset scenarios, mostly because of possible
configuration change.The used mechanism is taken from the km_kirkwood design and adapted to
the kmp204x case (slightly different HW and PCIe configuration).Signed-off-by: Valentin Longchamp
Reviewed-by: York Sun -
On the previous HW revision (now unsupported), there was a need for
external DMA signals and thus the I2C3/4 signals were used
DMA1_DONE/ACK/REQ.These signals now are configured as GPIO[16:19].
Signed-off-by: Valentin Longchamp
Reviewed-by: York Sun -
According to the errata, some bits of an undocumented register in the
DCSR must be set for every core in order to avoid a possible data or
instruction corruption.This is required for the 2.0 revision of the P2041 that should be used
as soon as available in our design.Signed-off-by: Valentin Longchamp
Reviewed-by: York Sun -
This patch adds support for using some GPIOs that are connected to the
I2C bus to force the bus lines state and perform some bus deblocking
sequences.The KM common deblocking algorithm from board/keymile/common/common.c is
used. The GPIO lines used for deblocking the I2C bus are some external
GPIOs provided by the QRIO CPLD:
- SCL = GPIOA_20
- SDA = GPIOA_21The QRIO GPIOs act in an open-drain-like manner, for 0 the line is
driven low and for 1 the GPIO is set as input and the line gets
pulled-up.Signed-off-by: Rainer Boschung
Signed-off-by: Valentin Longchamp
Reviewed-by: York Sun -
The QRIO GPIO functions can be of general interest. They are thus added
to a qrio.c and their prototype are available from kmp204x.h. The QRIO
prst function are also included in this file, as well as the functions
required for the I2C deblocking support (open-drain).Signed-off-by: Valentin Longchamp
[York Sun: Remove extra blank line in board/keymile/kmp204x/qrio.c]
Signed-off-by: York Sun -
Make use of the QRIO1 32bit register at 0x20 as bootcounter register
Check for BOOTCOUNT_MAGIC pattern when before bootcounter value is readSigned-off-by: Rainer Boschung
Signed-off-by: Valentin Longchamp
[York Sun: Minor change to commit message]
Signed-off-by: York Sun -
This covers only non-L2 switch ethernet interfaces i.e.
RGMII and SGMII interface for both T1040RDB and T1042RDB_PIT1040RDB is configured as serdes protocol 0x66 which can
support following interfaces
2 RGMIIS on DTSEC4, DTSEC5
1 SGMII on DTSEC3T1042RDB_PI is configured as serdes protocol 0x06 which can
support following interfaces
2 RGMIIS on DTSEC4, DTSEC5Signed-off-by: Poonam Aggrwal
Signed-off-by: Priyanka Jain
[York Sun: Minor change in commit message]
Signed-off-by: York Sun -
Enable entherent for T1040QDS. It enables FM1@DTSEC3, FM1@DTSEC4, FM1@DTSEC5
Define MDIO related configs
Added eth.c file
Update t1040.c to support RGMII and SGMII
Update t1040qds.c to support ethernet
Define the PHY addressSigned-off-by: Arpit Goel
Signed-off-by: Bhupesh Sharma
Signed-off-by: Poonam Aggrwal
Signed-off-by: Priyanka Jain
Signed-off-by: Prabhakar Kushwaha
[York Sun: remove dash from commit message]
Signed-off-by: York Sun -
Due to increased size of u-boot, FMAN ucode start address has been shifted
by 256KB causing a overlap with rootfs start address.Update rootfs start address to reflect correct memory map.
Also fix minor typo in README
Signed-off-by: Prabhakar Kushwaha
Reviewed-by: York Sun
30 Jan, 2014
1 commit
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If CONFIG_CFI_FLASH_MTD is not defined, then we shouldn't perform the
flash early reset.This commit fixes the following build error:
nios2-generic.c: In function `__early_flash_cmd_reset':
nios2-generic.c:23: error: `AMD_CMD_RESET' undeclared (first use in this function)
nios2-generic.c:23: error: (Each undeclared identifier is reported only once
nios2-generic.c:23: error: for each function it appears in.)
nios2-generic.c:24: error: `FLASH_CMD_RESET' undeclared (first use in this function)which was introduced by:
commit a113fb39df43546c704aa8eba55720da9a9dfedd
Author: Ezequiel Garcia
Date: Fri Dec 20 18:34:53 2013 -0300board: nios2: Add CONFIG_CFI_FLASH_MTD guard to flash.h header include
Signed-off-by: Ezequiel Garcia
Cc: Thomas Chou
Reported-by: Masahiro Yamada
Signed-off-by: Ezequiel Garcia
25 Jan, 2014
5 commits
-
Delete some serial.h files, whole code in which is surrounded by
#if 0 ... #endifSigned-off-by: Masahiro Yamada
Acked-by: Stefan Roese -
Commit e5c5301f refactored the build system not to make
directories in board makefiles.
But commit 8f380381 create directories again in
board/avionic-design/tec-ng/Makefile.Signed-off-by: Masahiro Yamada
Cc: Alban Bedel -
Signed-off-by: Masahiro Yamada
Acked-by: Stefan Roese
Acked-by: Matthias Fuchs -
Commit 643aae1406c93ddc64fcf8c136b47cdffd9c8ccd
deleted include/linux/config.h but missed to
delete _LINUX_CONFIG_H macro.
It is no longer used at all.Signed-off-by: Masahiro Yamada
-
If timer_init() is made a weak stub function, then it allows us to
remove several empty timer_init functions for those boards that
already have a timer initialized when u-boot starts. Architectures
that use the timer framework may also remove the need for timer.c.Signed-off-by: Darwin Rambo
Reviewed-by: Tim Kryger
23 Jan, 2014
1 commit
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On BSC9131, BSC9132, P1010 : For High Capacity SD Cards (> 2 GBytes), the
32-bit source address specifies the memory address in block address
format. Block length is fixed to 512 bytes as per the SD High Capacity
specification. So we need to convert the block address format
to byte address format to calculate the envaddr.If there is no enough space for environment variables or envaddr
is larger than 4GiB, we relocate the envaddr to 0x400. The address
relocated is in the front of the first partition that is assigned
for sdboot only.Signed-off-by: Haijun Zhang
Acked-by: Pantelis Antoniou
Reviewed-by: York Sun
22 Jan, 2014
5 commits
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u-boot binary size for Freescale mpc85xx platforms is 512KB.
This has been reached to upper limit for some of the platforms causig
linker error.So, Increase the u-boot binary size to 768KB.
Signed-off-by: York Sun
Signed-off-by: Prabhakar Kushwaha -
- Optimize UDIMM parameters for whole range from 1500MT/s to 2140MT/s.
- Remove unused patameters: 'cpo', 'wrdata delay', '2T', which are
unrelated to DDR3/3L.Tested with UDIMM 9JSF25672AZ-2G1K1 and verified speed 1200/1866/2133MT/s.
Signed-off-by: Shengzhou Liu
Reviewed-by: York Sun -
Using the TPL/SPL method to booting from 8k page NAND flash.
- Add 256kB size SRAM tlb for second step booting;
- Add spl.c for TPL image boot;
- Add spl_minimal.c for minimal SPL image;
- Add C29XPCIE_NAND configure;
- Modify C29XPCIE.h for nand config and enviroment;Signed-off-by: Po Liu
Reviewed-by: York Sun -
- add more serdes protocols support.
- fix some serdes lanes route.
- fix SGMII doesn't work and incorrect mdio display for XFI when serdes 0x6d.
- correct boot location info for SD/SPI boot.Signed-off-by: Shengzhou Liu
Reviewed-by: York Sun -
Update following DDR related settings for T1040QDS
-Correct number of chip selects to two as t1040qds supports
two Chip selects.
-Update board_specific_parameters udimm structure with settings
derived via calibration.
-Reduced I2C speed to 50KHz as DDR-SPD does not get reliably
read at 400KHz.Verified the updated settings to be working fine with dual-ranked
Micron, MT18KSF51272AZ-1G6 DIMM at data rate 833MT/s, 1333MT/s and
1600MT/s.Signed-off-by: Poonam Aggrwal
Signed-off-by: Priyanka Jain
Reviewed-by: York Sun
21 Jan, 2014
1 commit
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Send RPC commands to the VideoCore to turn on the SDHCI and USB modules.
For SDHCI this isn't needed in practice, since the firmware already
turned on the power in order to load U-Boot. However, it's best to be
explicit. For USB, this is necessary, since the module isn't powered
otherwise. This will allow the kernel USB driver to work.Signed-off-by: Stephen Warren
20 Jan, 2014
1 commit
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Universal uses only one adapter I2C_0.
Signed-off-by: Piotr Wilczek
Signed-off-by: Kyungmin Park
Acked-by: Przemyslaw Marczak
17 Jan, 2014
1 commit
16 Jan, 2014
2 commits
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On U-boot uses TMU0 as timer, but TMU0 does not use on linux kernel
and other.
This disables TMU0 at the request of from kernel user.Signed-off-by: Nobuhiro Iwamatsu
Signed-off-by: Nobuhiro Iwamatsu -
On U-boot uses TMU0 as timer, but TMU0 does not use on linux kernel
and other.
This disables TMU0 at the request of from kernel user.Signed-off-by: Nobuhiro Iwamatsu
Signed-off-by: Nobuhiro Iwamatsu
15 Jan, 2014
4 commits
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SolidRun has designed the Hummingboard board based on mx6q/dl/solo.
Add the initial support for the mx6 solo variant.
More information about this hardware can be found at:
http://imx.solid-run.com/wiki/index.php?title=Carrier-One_Hardware(Carrier-One was the previous name of Hummingboard).
Based on the work from Jon Nettleton .
Signed-off-by: Jon Nettleton
Signed-off-by: Fabio Estevam -
Provide an argument to enable_fec_anatop_clock() to specify the clock frequency
that will be generated.No changes are made to mx6slevk, which uses the default 50MHz fec clock.
Signed-off-by: Fabio Estevam
Acked-by: Stefano Babic
14 Jan, 2014
2 commits
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Signed-off-by: Ezequiel Garcia