24 Oct, 2019
1 commit
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Since commit c98b47f1ff60 ("MLK-22749 imx8mq: Add workaround to fix sticky
bits lock up") it's not possible to build i.MX8MM and i.MX8MN targets with
CONFIG_SECURE_BOOT enabled:CC cmd/version.o
arch/arm/mach-imx/imx8m/soc.c:326:23: error: ‘CONFIG_IMX_UNIQUE_ID’ undeclared \
(first use in this function); did you mean ‘CONFIG_IMX_VIDEO_SKIP’?
if (!is_uid_matched(CONFIG_IMX_UNIQUE_ID))
^~~~~~~~~~~~~~~~~~~~The OCOTP sticky bit workaround is only needed for i.MX8MQ devices, other devices
should not build the secure_lockup() function.Add CONFIG_IMX8MQ to the conditional compilation to avoid such issue.
Fixes: c98b47f1ff60 ("MLK-22749 imx8mq: Add workaround to fix sticky bits lock up")
Signed-off-by: Breno Lima
Reviewed-by: Ye Li
(cherry picked from commit be033bff3c718e8bd7d4ac5ecfe4361892fc6e61)
15 Oct, 2019
3 commits
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Latest SCFW has removed old MISC SECO commands. So update the codes
to use new SECO commands.Signed-off-by: Ye Li
Reviewed-by: Peng Fan
(cherry picked from commit 8e54efce6d2a1691605ae23983ff91f4a702adba) -
flash in u-boot for imx8mm-evk
imx8mm-evk uses BCH encoding and randomizer
modify macro and print size_t with %zx
use CONFIG_IMX8M because it should apply to imx8mq/mm/mn
Signed-off-by: Alice Guo
(cherry picked from commit 8d95b51fd70be29ef6beaa0f65c101b329f04f8e) -
dependency of CMD_NANDBCB`s default value
compiling nandbcb of imx8mm-evk depends on NAND and CMD_MTDPARTS
modify dependency of CMD_NANDBCB`s default value
Signed-off-by: Alice Guo
(cherry picked from commit 1b14e8cbefdb0f8126ceb6a85b1fd0db142328e6)
11 Oct, 2019
4 commits
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Current flexspi driver enables the Quad DTR read, so the measured
100Mhz SCLK is actually for DTR mode not SDR. However, according to
MT25QU256ABA datasheet, this flash only supports max DTR at 90Mhz and
max SDR at 166Mhz. It means current clock setting violate the flash
spec. So change back the flexspi clock to align with imx8mm.Signed-off-by: Ye Li
Reviewed-by: Peng Fan
(cherry picked from commit 3bf41bae974003550b70ea1a8b44ccb3117d818f)
(cherry picked from commit 4a369b527c3842751a4edf0171562a0e40c331ba) -
On B1 chips with HAB v4.4, the sticky bits are not locked up in
HAB closed mode. We introduce a workaround in SPL to lock up
these bits and clear Manufacturing Protection Private Key for
secure boot.For field return case, user has to build a SPL with
CONFIG_SECURE_STICKY_BITS_LOCKUP=n and set CONFIG_IMX_UNIQUE_ID to
part's unique id. When the UID check is passed, sticky bits are not
lockup and users can burn field return fuse. Otherwise the boot will
stop.Signed-off-by: Ye Li
(cherry picked from commit c98b47f1ff60e1f99807e24fd76053ad880f803e) -
Add REVC informaiton.
Signed-off-by: Frank Li
(cherry picked from commit c7231f2c7a5c1dc754b5fb9bf05941141877a0ec)
(cherry picked from commit 9a33170a4f4ff2ad2ab0d87e74e722a0e833abaa) -
bchtype in FCB should be associated to the gf_13/14 settings in BCH, fix
the issue and test on Micron 29F64G08CBABB, it can boot after the
change.Signed-off-by: Han Xu
(cherry picked from commit 9cc7bf9b17565b4e0d73acd690e32394034dfae2)
29 Sep, 2019
5 commits
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ROM SError happens on two cases:
1. ERR050342, on iMX8MQ HDCP enabled parts ROM writes to GPV1 register, but
when ROM patch lock is fused, this write will cause SError.2. ERR050350, on iMX8MQ/MM/MN, when the field return fuse is burned, HAB
is field return mode, but the last 4K of ROM is still protected and cause SError.Since ROM mask SError until ATF unmask it, so then ATF always meets the exception.
This patch works around the issue in SPL by enabling SPL Exception vectors table
and the SError exception, take the exception to eret immediately to clear the SError.Signed-off-by: Ye Li
Reviewed-by: Peng Fan
(cherry picked from commit f05dd45251ca82cc54e13a616f00744c26faab53)
(cherry picked from commit 25d059411e702a4002f1aa157839001f796dd9f6) -
Sometimes we met SERROR, but only to catch it when Linux boots up.
Let's enable catching in U-Boot to catch it ealier and ease debug.Signed-off-by: Peng Fan
(cherry picked from commit 7a0c9b08886e5dc7d50e640ed56eed0fe612161f)
(cherry picked from commit 33da22c4793e56077033a4f6c567894badb8e907)
(cherry picked from commit 4da3e872b7c61b93fa227935a7b45eb5fcb252e1) -
Add subcommand for add writing BCB only, where we provide appropriate
offsets for firmware1 and firmware2 and size.Example of usage:
> nandbcb bcbonly 0x00180000 0x00080000 0x00200000
Writing 1024 bytes to 0x0: randomizing
OK
Writing 1024 bytes to 0x20000: randomizing
OKSigned-off-by: Igor Opaniuk
(cherry picked from commit 353a38576ed6f21431bf499a4b402a5ca571f0fa) -
Move code for writing FCB/DBBT pages to a separate function
Signed-off-by: Igor Opaniuk
(cherry picked from commit c4e8b725681c9e7d18845260ac1061aedb9166a4) -
Add support for updating FCB/DBBT on i.MX7:
- additional new fields in FCB structure
- Leverage hardware BCH/randomizer for writing FCBSigned-off-by: Igor Opaniuk
Signed-off-by: Alice Guo
(cherry picked from commit b4b3049b1e4a069e522a1112bf4f9e0253836b2d)
23 Sep, 2019
1 commit
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Update the mx7ulp wdog disable sequence to avoid potential reset issue
in unlock or refresh sequence. Both sequence need two words write
to wdog CNT register in 16 bus clocks window, if miss the window,
the write will cause violation in wdog and reset the chip.Current u-boot code is using writel() function which has a DMB barrier
to order the memory access. The DMB between two words write may introduce
some delay in certain circumstance, causing the wdog reset due to 16 bus
clock window requirement.This patch replaces writel() function by __raw_writel() to avoid such issue,
and improve to check if watchdog is already disabled or unlocked.Signed-off-by: Ye Li
Tested-by: Breno Lima
Reviewed-by: Peng Fan
(cherry picked from commit b8c99d5f5bcc5573d3394b68890db16b6bb5fc88)
11 Sep, 2019
2 commits
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When enable u-boot splash screen and set kernel dtb with -hdmi.dtb on
imx8qm, the kernel reboot (partition reboot) will hang in u-boot if HDMI
cable is plugged in.
The root cause is kernel set the clock source of DC0 display0 channel to
bypass clock, when doing reboot this clock setting may not be cleared. So
u-boot has wrong clock source and cause lpcg stop bit always set.Fix the issue by adding the clock parent setting and not depend on default
parent value.Signed-off-by: Ye Li
Reviewed-by: Peng Fan
(cherry picked from commit 104c4b5cdc83fb671c6474708bdd00c2dfb01113)
(cherry picked from commit 8a287c629018e6bf647c3c617fca3e6c94a3d2a4) -
Have missed the lpcg settings when porting to 2019.04 u-boot
Signed-off-by: Ye Li
Reviewed-by: Peng Fan
(cherry picked from commit 4096d7806a0dcc501123c8c2cdf734620e37d169)
30 Aug, 2019
2 commits
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The dash-linux tree has dropped pd tree, so we could not get the reg.
The power-doamins property has a cell indicating the resource id,
let's use it for sid programming.Signed-off-by: Peng Fan
Reviewed-by: Ye Li -
Upstream kernel refactors the power domain nodes and the usage of
power-domains property in DTB. So when checking available resources
in AP partition with this kernel DTB, u-boot will reports some
warnings.
This patch will support both two power domain designs during updating
kernel DTB.Signed-off-by: Ye Li
Reviewed-by: Peng Fan
12 Aug, 2019
1 commit
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Like iMX8MM, iMX8MN also needs SW to load TMU TASR and TCALIV registers
value from fuse before enabling TMU calibration. Otherwise the calibration
is not exact.Signed-off-by: Ye Li
Reviewed-by: Anson Huang
(cherry picked from commit 9fb7f904ff6a03e2951a770daba12a522373c8ae)
09 Aug, 2019
2 commits
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The DM iMX PCI driver has DM_FLAG_OS_PREPARE set and will call
imx_pcie_remove() from the .remove callback. Do not call it from
the architecture code again.Signed-off-by: Marek Vasut
Cc: Bin Meng
Cc: Fabio Estevam
Cc: Stefano Babic
Reviewed-by: Bin Meng
(cherry picked from commit 42dc1230cdec48d0278dcc683bc14527cbea12c5) -
On imx8 platform, the usb2 and usb3 ports are both supported. Which
means we can use usb2(ci_udc_otg) and usb3(cdns3_generic_peripheral)
gadget driver to run sdp/fastboot/ums at the same time.For sdp and the fastboot that runs automatically when uboot starts,
board_usb_gadget_port_auto() is added to autodetect usb port, this
means that we don't have to specify which USB port should be used to
download in code, now we can just connect either usb port then it
will download automatically.Signed-off-by: Sherry Sun
01 Aug, 2019
1 commit
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We may need to enable the dual bootloader feature on non-trusty
platforms, skip the bootloader rollback index check in spl if
trusty is not enabled.Don't generate rpmb key in spl, it should be generated in u-boot
proper with u-boot commands.Test: dual bootloader on imx8mm.
Change-Id: Iac454e0140cd6f4472a66d267d9ba0d40df7102c
Signed-off-by: Ji Luo
31 Jul, 2019
1 commit
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The iMX8DXL phantom chip is 15x15 iMX8QXP, so we will use 8QXP as SOC,
add configs and codes for the new board.Signed-off-by: Ye Li
30 Jul, 2019
1 commit
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There is an divider on imx8mn will always divide 2 to flexspi root clock.
So actual SCLK output to device is 50Mhz on imx8mn not 100Mhz.After changing the root clock setting to configure SCLK to 100Mhz, found
the read data is not correct. Must enable the internal DQS pad loopback
to fix the problem.Signed-off-by: Ye Li
Reviewed-by: Peng Fan
(cherry picked from commit 9ff3ae4f9ebbb81bd42d81729cec4525c6e9b33e)
26 Jul, 2019
2 commits
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Since we remove SATA device before boot OS, when AHCI is enabled, update
the codes to remove AHCI device.Signed-off-by: Ye Li
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We reuse current sata clock interface in imx AHCI for imx6q/qp. So
enable them when the config is setSigned-off-by: Ye Li
25 Jul, 2019
1 commit
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Add new keymaster commands to get Manufacure Production key (mppubk).
Since the mppubk can only be generated in OEM CLOSED imx8q board, so
we can only use this command when the board is HAB/AHAB closed.Commands to extract the mppubk:
* $fastboot oem get-mppubk
* $fastboot get_staged mppubk.binTest: Generate and dump the mppubk.bin
Change-Id: Idc59e78ca6345497e744162664b8293f50d1eda4
Signed-off-by: Ji Luo
24 Jul, 2019
1 commit
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new imx8mn chips have Cortex-M7 inside, not like other imx8m devices
of imx8mm and imx8mq which have Cortex-M4 inside. the names of MACROs
used to boot MCU on imx8m devices is modified to make them more common
to cover M4 and M7.
annotations are also modified based on the differences between M4 and
M7.Change-Id: Ida272e6ecdf577eeaadb9f1242f4524bd1014cac
Signed-off-by: faqiang.zhu
17 Jul, 2019
1 commit
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To use one defconfig for all boot device, we have to runtime set
env offset and return env medium according to the boot device.
This patch overrides the env_get_offset and env_get_location to
implement the feature.Signed-off-by: Ye Li
(cherry picked from commit c25239a695feaad68051bab3ef098eef31d07f09)
16 Jul, 2019
2 commits
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Writing/updating boot image in nand device is not
straight forward in i.MX6 platform and it requires
boot control block(BCB) to be configured.It becomes difficult to use uboot 'nand' command to
write BCB since it requires platform specific attributes
need to be taken care of.It is even difficult to use existing msx-nand.c driver by
incorporating BCB attributes like mxs_dma_desc does
because it requires change in mtd and nand command.So, cmd_nandbcb implemented in arch/arm/mach-imx
BCB contains two data structures, Firmware Configuration Block(FCB)
and Discovered Bad Block Table(DBBT). FCB has nand timings,
DBBT search area, page address of firmware.On summary, nandbcb update will
- erase the entire partition
- create BCB by creating 2 FCB/DBBT block followed by
1 FW block based on partition size and erasesize.
- fill FCB/DBBT structures
- write FW/SPL on FW1
- write FCB/DBBT in first 2 blocksfor nand boot, up on reset bootrom look for FCB structure in
first block's if FCB found the nand timings are loaded for
further reads. once FCB read done, DTTB will load and finally
firmware will be loaded which is boot image.Refer section "NAND Boot" from doc/imx/common/imx6.txt for more usage
information.Signed-off-by: Jagan Teki
Signed-off-by: Sergey Kubushyn
Signed-off-by: Shyam Saini
Signed-off-by: Han Xu -
Add Kconfig entry for CMD_NANDBCB, and default y on i.MX6
platform with NAND_MXS defined.Reviewed-by: Stefano Babic
Signed-off-by: Jagan Teki
Signed-off-by: Shyam Saini
Signed-off-by: Han Xu
15 Jul, 2019
4 commits
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Add support for new target imx8mq_aiy.
Test: build and boot ok on imx8mq_aiy.
Change-Id: Ie616c3ae5fc5273036e975acd88fccfa8c5c95ee
Signed-off-by: Ji Luo -
Add board level support for android and android auto. Each board has
android/andriod_auto specified header file for defining relevant configuraitons.
And add build targets for their android uboot images building.Change-Id: Ib7c10404dbca9237ab074427d3cb10d98bfc0ed9
Signed-off-by: Ye Li -
this commit is a merge of three patches from imx_v2018.03 as below:
1.
commit dbcf1e3cc079d2f1b3df6c4c9ec3a34d0c05eb4c
Author: Luo Ji
Date: Fri Jun 8 10:31:11 2018 +0800[iot] Support dual bootloader in SPL
Move the A/B slot check to SPL, the A/B slot switch
workflow is just like what we have in libavb_ab.Test: A/B select works fine on imx8m.
2.
commit 71562aae3b8123ccd7503e596e478951568fcd24
Author: Ji Luo
Date: Mon Jan 14 18:28:08 2019 +0800MA-13938 [Android] imx8q: Support dual bootloader feature
Support dual bootloader feature for imx8q which uses the
container format. Move the A/B slot select and verify to
SPL stage, the bootloader rollback index will be stored
at the last 8K bytes of eMMC rpmb storage.Test: Boot and rbindex verify pass on imx8q.
Change-Id: Ic9410a48092cc05de599dd897fc912177e2a1fe1
Signed-off-by: faqiang.zhu -
imx8mn speed grade fuse uses new definitions as below. So have
to update get_cpu_speed_grade_hz function to match it.SPEED_GRADING[5:0]:
SPEED_GRADE[5:4] SPEED_GRADE[3:0] MHz
xx 0000 2300
xx 0001 2200
xx 0010 2100
xx 0011 2000
xx 0100 1900
xx 0101 1800
xx 0110 1700
xx 0111 1600
xx 1000 1500
xx 1001 1400
xx 1010 1300
xx 1011 1200
xx 1100 1100
xx 1101 1000
xx 1110 900
xx 1111 800Signed-off-by: Ye Li
(cherry picked from commit e4e9ba2e868ea1b55581bdc1b7096cfb9cc15009)
10 Jul, 2019
2 commits
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Add DEK encapsulation support for imx8. The DEK blob is generated by the
SECO through the SCFW API.Signed-off-by: Clement Faure
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The commit "MLK-22219 mx6: Place pre_misc_setting() into a common location"
causes iMX6QP boot hang. Because QoS settings in pre_misc_setting depends on
IPU and PRG clocks enabled.
So still calling pre_misc_setting in enable_ipu_clock, and move
enable_ipu_clock to arch_cpu_initSigned-off-by: Ye Li
09 Jul, 2019
3 commits
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Add DEK blob encapsulation support for IMX8M through "dek_blob" command.
On ARMv8, u-boot runs in non-secure, thus cannot encapsulate a DEK blob
for encrypted boot.
The DEK blob is encapsulated by OP-TEE through a trusted application call.
U-boot sends and receives the DEK and the DEK blob binaries through OP-TEE
dynamic shared memory.To enable the DEK blob encapsulation, add to the defconfig:
CONFIG_SECURE_BOOT=y
CONFIG_FAT_WRITE=y
CONFIG_CMD_DEKBLOB=ySigned-off-by: Clement Faure
Reviewed-by: Ye Li -
According to datasheet, there are totally 6 variant parts for imx8mn:
Quad, Dual, Solo with core number changed.
QuadLite, DualLite, SoloLite with core number changed and GPU disabled.Add the support for these variant parts
1. Recognize the variant parts according to fuse
2. Power down disabled cores
3. Remove the cores node and disable GPU node from kernel DTB before
entering kernel.
4. Since the mscale dummy id has been used out, increase one more bit
(bit 8) for cpu id.Signed-off-by: Ye Li
Reviewed-by: Peng Fan
(cherry picked from commit 144bd9ce223ead71e1726bea510242a3166f66ce) -
Add imx8mn_ddr4_evk_nom_defconfig to generate SPL and u-boot to force SOC
to nominal mode. So the VDD_SOC will be 0.85V and ARM will be fixed to 0.85V
with DVFS disabled in kernel.Signed-off-by: Ye Li
Acked-by: Anson Huang
(cherry picked from commit 0dca81742f51141ce0fb2117cbc1e99b84945009)