16 Sep, 2017

1 commit

  • This adds support to Intel Cherry Hill board, a board based on
    Intel Braswell SoC. The following devices are validated:

    - serial port as the serial console
    - on-board Realtek 8169 ethernet controller
    - SATA AHCI controller
    - EMMC/SDHC controller
    - USB 3.0 xHCI controller
    - PCIe x1 slot with a graphics card
    - ICH SPI controller with an 8MB Macronix SPI flash
    - Integrated graphics device as the video console

    Signed-off-by: Bin Meng
    Reviewed-by: Simon Glass

    Bin Meng
     

15 Sep, 2017

13 commits


13 Sep, 2017

10 commits


12 Sep, 2017

11 commits


11 Sep, 2017

5 commits

  • Enabled PCIe support and PCI command feature.

    Signed-off-by: Hou Zhiqiang
    Reviewed-by: York Sun

    Hou Zhiqiang
     
  • This patch adds support for RGMII protocol

    NXP's LDPAA2 support RGMII protocol. LS1088A is the
    first Soc supporting both RGMII and SGMII.

    Signed-off-by: Prabhakar Kushwaha
    Signed-off-by: Amrita Kumari
    Signed-off-by: Ashish Kumar
    Reviewed-by: York Sun

    Ashish Kumar
     
  • This patch add support of LS1088AQDS platform.

    The LS1088A QorIQTM Development System (QDS) is a high-performance
    computing, evaluation, and development platform that supports the
    LS1088A QorIQ Architecture processor.

    Signed-off-by: Prabhakar Kushwaha
    Signed-off-by: Shaohui Xie
    Signed-off-by: Ashish Kumar
    Reviewed-by: York Sun

    Ashish Kumar
     
  • LS1088A is an ARMv8 implementation. The LS1088ARDB is an evaluatoin
    platform that supports the LS1088A family SoCs. This patch add basic
    support of the platform.

    Signed-off-by: Alison Wang
    Signed-off-by: Prabhakar Kushwaha
    Signed-off-by: Ashish Kumar
    Signed-off-by: Raghav Dogra
    Signed-off-by: Shaohui Xie
    [YS: Disabled NAND in board header file]
    Reviewed-by: York Sun

    WIP: disable NAND for LS1088ARDB

    Ashish Kumar
     
  • CoreLink Cache Coherent Interconnect (CCI) provides full cache
    coherency between two clusters of multi-core CPUs and I/O coherency
    for devices and I/O masters.

    This patch add new config option SYS_FSL_HAS_CCI400 and moves
    existing register space definaton of CCI-400 bus to fsl_immap to be
    shared. CONFIG_SYS_CCI400_ADDR is replaced with SYS_CCI400_OFFSET
    in Kconfig.

    Signed-off-by: Ashish Kumar
    Signed-off-by: Prabhakar Kushwaha
    [YS: revised commit message, squashed patches for armv8 and armv7]
    Reviewed-by: York Sun

    Ashish Kumar