10 May, 2014
4 commits
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Signed-off-by: Masahiro Yamada
Cc: Simon Glass
Acked-by: Simon Glass -
Prior to commit 33a02da0, all boards must have board/${BOARD}/
or board/${VENDOR}/${BOARD}/ directory.
Now this rule is obsolete.It looks weird that sandbox defines "vendor" and "board" just for
meeting the old U-Boot directory structure.Signed-off-by: Masahiro Yamada
Cc: Simon Glass -
Some machines do not have SDL libraries installed, and it is still useful
to build sandbox without LCD/keyboard support.Add an option for this, used as follows:
make sandbox_config all NO_SDL=1
Signed-off-by: Simon Glass
09 May, 2014
4 commits
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Conflicts:
drivers/net/Makefile(trivial merge)
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Without this patch SPARC/LEON does not build.
Reported-by: Tom Rini
Signed-off-by: Daniel Hellstrom -
Before it was hardcoded to 1000 ticks per second.
Signed-off-by: Daniel Hellstrom
07 May, 2014
1 commit
30 Apr, 2014
2 commits
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The rmobile SoC has usb host controller.
This supports USB controllers listed in the R8A7790, R8A7791 and R8A7740.Signed-off-by: Nobuhiro Iwamatsu
Reviewed-by: Marek Vasut -
Signed-off-by: Masahiro Yamada
Cc: Nobuhiro Iwamatsu
Acked-by: Nobuhiro Iwamatsu
Signed-off-by: Nobuhiro Iwamatsu
26 Apr, 2014
2 commits
24 Apr, 2014
1 commit
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mpc831x has no muram, so muram cannot be used for bootcounter
function.Signed-off-by: Heiko Schocher
Signed-off-by: Kim Phillips
23 Apr, 2014
26 commits
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B4420 is a personality of B4860.
It should have same FM1_CLK_SEK and FM1_CLK_SHIFT as B4860Signed-off-by: Prabhakar Kushwaha
Reviewed-by: York Sun -
Adds support for clock sourcing from sysclk(100MHz) for usb
on T104xRDB and T1040QDS. This requires changing reference divisor
and multiplication factor to derive usb clock from sysclk.Signed-off-by: Nikhil Badola
Reviewed-by: York Sun -
T1040 and it's variants provide "Single Oscillator Source" Reference Clock Mode.
In this mode, single onboard oscillator(DIFF_SYSCLK) can provide the reference clock
(100MHz) to the following PLLs:
• Platform PLL
• Core PLLs
• USB PLL
• DDR PLL, etcThe cfg_eng_use0 of porsr1 register identifies whether the SYSCLK (single-ended) or
DIFF_SYSCLK (differential) is selected as the clock input to the chip.get_sys_info has been enhanced to add the diff_sysclk so that the
various drivers can be made aware of ths diff sysclk configuration and
act accordingly.Other changes:
-single_src to ddr_refclk_sel, as it is use for checking ddr reference clock
-Removed the print of single_src from get_sys_info as this will be
-printed whenever somebody calls get_sys_info which is not appropriate.
-Add print of single_src in checkcpu as it is called only once during initializationSigned-off-by: Poonam Aggrwal
Signed-off-by: Priyanka Jain
Signed-off-by: Vijay Rai
Reviewed-by: York Sun -
It is not necessary for bootpg to be present at text + 512KB.
With increase of u-boot size (768KB), bootpg section's address
cannot be fixed.Signed-off-by: Prabhakar Kushwaha
Reviewed-by: York Sun -
Before parsing LAW table i.e. init_law, boot loader should disable all
previous LAWs except DDR LAWs which has been created by previous
pre boot loader during DDR initialization.Signed-off-by: Prabhakar Kushwaha
Reviewed-by: York Sun -
Current SPL code base has BSS section placed after reset_vector. This means
they have to relocate to use the global variables. This put an implicit
requirement of having SPL size = Memory/2.To avoid relocation:
- Move bss_section within SPL range
- Modify relocate_code()Signed-off-by: Prabhakar Kushwaha
Reviewed-by: York Sun -
SPL linker has fix location of bootpg and reset vector with respect to text base.
It is not necessary to have fixed locations.Avoid such hardcoding.
Signed-off-by: Prabhakar Kushwaha
Reviewed-by: York Sun -
LAW_EN is only defined if CONFIG_SYS_CCSRBAR_DEFAULT is not equal to
CONFIG_SYS_CCSRBAR_PHYS. in SPL framework CCSRBAR is not relocated hence
both are same. This cause compilation error.So LAW_EN define outside of configs
Signed-off-by: Prabhakar Kushwaha
Reviewed-by: York Sun -
qe_init() does not use data copied from NAND. Thise code is not tested or
complied causing compilation error during NAND bootSo, remove QE firmware copy from NAND to ddr.
Signed-off-by: Prabhakar Kushwaha
Reviewed-by: York Sun -
When T104x soc wakes up from deep sleep, control is passed to the
primary core that starts executing uboot. After re-initialized some
IP blocks, like DDRC, kernel will take responsibility to continue
to restore environment it leaves before.Signed-off-by: Tang Yuantian
Reviewed-by: York Sun -
The supplement configuration unit (SCFG) provides chip-specific
configuration and status registers for the device. It is the chip
defined module for extending the device configuration unit (DCFG)
module. It provides a set of CCSR registers in addition to those
available in the device configuration unit.
The base address for this unit is 0x0F_C000.Signed-off-by: Tang Yuantian
Reviewed-by: York Sun -
T1040RDB and T1040QDS boards have an integrated l2 switch.
The switch needs a MAC address for Layer 2 protocols
(MSTP, LLDP, LACP, etc). Setting a MAC address on l2switchaddr will add
a MAC in device-tree, under node l2switch.Signed-off-by: Codrin Ciubotariu
Cc: York Sun
Reviewed-by: York Sun -
Erratum A007212 for DDR is about a runaway condition for DDR PLL
oscilliator. Please refer to erratum document for detail.
For this workaround to work, DDR PLL needs to be disabled in RCW.
However, u-boot needs to know the expected PLL ratio. We put the
ratio in a reserved field RCW[18:23]. U-boot will skip this workaround
if DDR PLL ratio is set, or the reserved field is not set.Workaround for erratum A007212 applies to selected versions of
B4/T4 SoCs. It is safe to apply the workaround to all versions. It
is helpful for upgrading SoC without changing u-boot. In case DDR
PLL is disabled by RCW (part of the erratum workaround), we need this
u-boot workround to bring up DDR clock.Signed-off-by: York Sun
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Put a delay of 5 millisecond after reset so that ULPI phy
gets enough time to come out of reset. Erratum A007075 applies
to following SOCs and their variants, if any
P1010 rev 1.0
B4860 rev 1.0, 2.0
P4080 rev 2.0, 3.0Signed-off-by: Nikhil Badola
Reviewed-by: York Sun -
Mostly reusing DDR3 driver, this patch adds DDR4 SPD handling, register
calculation and programming.Signed-off-by: York Sun
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The value written to L2CSR1 didn't match the value written to the
device tree.Signed-off-by: Scott Wood
Reviewed-by: York Sun -
Modify code to adapt to both u-qe and qe.
U_QE is a kind of cutted QE.
the differences between U_QE and QE
1. UCC: U_QE supports 2 UCCs while QE supports up to 8 UCCs.
2. IMMR: have different immr base addr.
3. iopin: U_QE doesn't need to config iopin.Signed-off-by: Zhao Qiang
Reviewed-by: York Sun -
CONFIG_SYS_QE_FMAN_FW_ADDR is used to both Fman and QE for microcode address.
Now using CONFIG_SYS_FMAN_FW_ADDR for Fman microcode address,
and CONFIG_SYS_QE_FW_ADDR for QE microcode address.Signed-off-by: Zhao Qiang
Reviewed-by: York Sun -
Secure Boot Target is added for T1040QDS and T1040RDB
Changes:
For Secure boot, CPC is configured as SRAM and used as house
keeping area which needs to be disabled.
So CONFIG_SYS_CPC_REINIT_F is defined for CONFIG_T1040QDS and
CONFIG_T1040RDBSigned-off-by: Gaurav Rana
Signed-off-by: Aneesh Bansal
Reviewed-by: York Sun -
Secure Boot Target is added for T2080QDS
Changes:
For Secure boot, CPC is configured as SRAM and used as house
keeping area which needs to be disabled.
So CONFIG_SYS_CPC_REINIT_F is defined for CONFIG_T2080QDS.Signed-off-by: Aneesh Bansal
Reviewed-by: York Sun -
Secure Boot Target is added for T4240QDS and T4160QDS
Changes:
For Secure boot, CPC is configured as SRAM and used as house
keeping area which needs to be disabled.
So CONFIG_SYS_CPC_REINIT_F is defined for CONFIG_T4240QDS.Signed-off-by: Aneesh Bansal
Reviewed-by: York Sun -
Changes:
1. L2 cache is being invalidated by Boot ROM code for e6500 core.
So removing the invalidation from start.S
2. Clear the LAW and corresponding configuration for CPC. Boot ROM
code uses it as hosekeeping area.
3. For Secure boot, CPC is configured as SRAM and used as house
keeping area. This configuration is to be disabled once in uboot.
Earlier this disabling of CPC as SRAM was happening in cpu_init_r.
As a result cache invalidation function was getting skipped in
case CPC is configured as SRAM.This was causing random crashes.Signed-off-by: Ruchika Gupta
Signed-off-by: Aneesh Bansal
Reviewed-by: York Sun -
Add NOR, SPI and SD secure boot targets for BSC9132QDS.
Changes:
- Debug TLB entry is not required for Secure Boot Target.Signed-off-by: Aneesh Bansal
Reviewed-by: York Sun -
ISBC creates a LAW 0 entry for non PBL platforms, which is not
disabled before transferring the control to uboot.
The LAW 0 entry has to be disabled.Signed-off-by: Aneesh Bansal
Reviewed-by: York Sun -
For KVM we have a special PV machine type called "ppce500". This machine
is inspired by the MPC8544DS board, but implements a lot less features
than that one.It also provides more PCI slots and is supposed to be enumerated by
device tree only.This patch adds support for the generic ppce500 machine and tries to
rely solely on device tree for device enumeration.Signed-off-by: Alexander Graf
Acked-by: Scott Wood
Reviewed-by: York Sun -
We want to be able to directly execute the ELF binary without going
through the u-boot.bin one.To know where we have to start executing this ELF binary we have to
tell the linker where our entry point is.Signed-off-by: Alexander Graf
Acked-by: Scott Wood
Reviewed-by: York Sun
