01 Aug, 2017
3 commits
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Only a specific type of SPI flash exists on a board, having board
Kconfig to select the SPI flash seems to make more sense. Other
flash types are not necessary except coreboot, which implies all
available flash drivers there.Signed-off-by: Bin Meng
Reviewed-by: Simon Glass -
This is architecture-dependent early initialization hence should
be put in the platform Kconfig.Signed-off-by: Bin Meng
Reviewed-by: Andy Shevchenko
Reviewed-by: Simon Glass -
CONFIG_BOARD_EARLY_INIT_F literally indicates board-specific codes
and should be not 'default y' for all x86 boards.Signed-off-by: Bin Meng
Reviewed-by: Andy Shevchenko
Reviewed-by: Simon Glass
07 Feb, 2017
2 commits
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Add a new board config which uses 64-bit U-Boot. This is not fully
functional but is it a start. Missing features:- SDRAM sizing
- Booting linux
- EFI support
- SCSI device init
(and others)Signed-off-by: Simon Glass
Reviewed-by: Bin Meng -
Set up the 64-bit U-Boot text base if building for that target.
Signed-off-by: Simon Glass
Reviewed-by: Bin Meng
17 Mar, 2016
1 commit
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We don't need this anymore - we can use device tree and the new pinconfig
driver instead.Signed-off-by: Simon Glass
Reviewed-by: Bin Meng
24 Jan, 2016
1 commit
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Instead of calling the northbridge and PCH init from bd82x6x_init_extra()
when the PCI bus is probed, call it from the respective drivers. Also drop
the Northbridge init as it has no effect. The registers it touches appear to
be read-only.Signed-off-by: Simon Glass
Reviewed-by: Bin Meng
13 Jan, 2016
1 commit
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Do not set HAVE_INTEL_ME by default as for some cases Intel ME
firmware even does not reside on the same SPI flash as U-Boot.Signed-off-by: Bin Meng
Acked-by: Simon Glass
Tested-by: Simon Glass
09 Dec, 2015
3 commits
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These are currently dead codes. Until we have complete ACPI support,
we don't know if it works or not. Remove to avoid confusion.Signed-off-by: Bin Meng
Acked-by: Simon Glass
Tested-by: Simon Glass -
This Kconfig option name indicates it has something to do with cpu
socket, however it is actually not the case. Remove it and move
options inside it to NORTHBRIDGE_INTEL_IVYBRIDGE.Signed-off-by: Bin Meng
Acked-by: Simon Glass
Tested-by: Simon Glass -
There are some options which are never used, and also some options
which are selected by others but have never been a Kconfg option.
Clean these up.Signed-off-by: Bin Meng
Acked-by: Simon Glass
Tested-by: Simon Glass
15 Jul, 2015
1 commit
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MARK_GRAPHICS_MEM_WRCOMB is not referenced anywhere in the code,
hence remove it.Signed-off-by: Bin Meng
Acked-by: Simon Glass
30 Apr, 2015
1 commit
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Currently all x86 boards still use CONFIG_SYS_EXTRA_OPTIONS to define
the text base address. Since it is deprecated, just remove it and use
CONFIG_SYS_TEXT_BASE directly.Signed-off-by: Bin Meng
Acked-by: Simon Glass
19 Apr, 2015
2 commits
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Since driver model will probe the EC when it is first used, we do not
need to init it explicitly.Signed-off-by: Simon Glass
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Move coreboot-x86 over to driver model for PCI.
Signed-off-by: Simon Glass
06 Feb, 2015
1 commit
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This setting will be used by more than just ivybridge so make it common.
Also rename it to PCIE_ECAM_BASE which is a more descriptive name.
Signed-off-by: Simon Glass
Reviewed-by: Bin Meng
13 Jan, 2015
2 commits
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Move CONFIG_SYS_CAR_ADDR and CONFIG_SYS_CAR_SIZE to Kconfig so that
we don't need them in the board configuration file thus the same
board configuratoin file can be used to build both coreboot version
and bare version.Signed-off-by: Bin Meng
Acked-by: Simon Glass -
Convert CONFIG_X86_RESET_VECTOR and CONFIG_SYS_X86_START16 to Kconfig
options so that we can remove them from board configuration file.Signed-off-by: Bin Meng
Acked-by: Simon Glass
19 Dec, 2014
1 commit
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Intel Tunnel Creek GPIO register block is compatible with current
ich6-gpio driver, except the offset and content of GPIO block base
address register in the LPC PCI configuration space are different.Use u16 instead of u32 to store the 16-bit I/O address of the GPIO
registers so that it could support both Ivybridge and Tunnel Creek.Signed-off-by: Bin Meng
Acked-by: Simon Glass
14 Dec, 2014
2 commits
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Movie setup_pch_gpios() in the ich6-gpio driver to the board support
codes, so that the driver does not need to know any platform specific
stuff (ie: include the platform specifc chipset header file).Signed-off-by: Bin Meng
Acked-by: Simon Glass -
Currently the ROM_SIZE is hardcoded to 8MB in arch/x86/Kconfig. This
will not be the case when adding additional board support. Hence we
make ROM_SIZE configurable (512KB/1MB/2MB/4MB/8MB/16MB) and have the
board Kconfig file select the default ROM_SIZE.Signed-off-by: Bin Meng
Acked-by: Simon Glass
25 Nov, 2014
2 commits
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Enable the Chrome OS EC so that it can be used from U-Boot.
Signed-off-by: Simon Glass
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This function is not needed. Remove it to improve the generic init sequence
slightly.Signed-off-by: Simon Glass
Reviewed-by: Bin Meng
21 Nov, 2014
4 commits
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Enable GPIO support and provide the required GPIO setup information to
the driver.Signed-off-by: Simon Glass
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Add support for CAR so that we have memory to use prior to DRAM init.
On link there is a total of 128KB of CAR available, although some is
used for the memory reference code.Signed-off-by: Simon Glass
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On x86 it is common to use 'post codes' which are 8-bit hex values emitted
from the code and visible to the user. Traditionally two 7-segment displays
were made available on the motherboard to show the last post code that was
emitted. This allows diagnosis of a boot problem since it is possible to
see where the code got to before it died.On modern hardware these codes are not normally visible. On Chromebooks
they are displayed by the Embedded Controller (EC), so it is useful to emit
them. We must enable this feature for the EC to see the codes, so add an
option for this.Signed-off-by: Simon Glass
Reviewed-by: Bin Meng -
This board is a 'bare' version of the existing 'link 'board. It does not
require coreboot to run, but is intended to start directly from the reset
vector.This initial commit has place holders for a wide range of features. These
will be added in follow-on patches and series. So far it cannot be booted
as there is no ROM image produced, but it does build without errors.Signed-off-by: Simon Glass