20 May, 2014
1 commit
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Clean up partial, full and compressed bitstream handling.
U-Boot supports full bitstream loading and partial
based on detection which is not 100% correct.
Extending fpga_load/fpga_loadbitstream() with one more
argument which stores bitstream type.Signed-off-by: Michal Simek
13 May, 2014
3 commits
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Connect FPGA version with appropriate operations
to remove huge switch-cases for every FPGA family.
Tested on Zynq. Spartan2/Spartan3/Virtex2 just compile test.Signed-off-by: Michal Simek
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No functional changes.
Signed-off-by: Michal Simek
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No functional changes.
Signed-off-by: Michal Simek
24 Jul, 2013
1 commit
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Signed-off-by: Wolfgang Denk
[trini: Fixup common/cmd_io.c]
Signed-off-by: Tom Rini
02 Apr, 2013
1 commit
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'bool' is defined in random places. This patch consolidates them into a
single header file include/linux/types.h, using stdbool.h introduced in C99.All other #define, typedef and enum are removed. They are all consistent with
true = 1, false = 0.Replace FALSE, False with false. Replace TRUE, True with true.
Skip *.py, *.php, lib/* files.Signed-off-by: York Sun
05 Jan, 2012
1 commit
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CONFIG_SYS_FPGA_PROG_FEEDBACK was already introduced to print
the current status of FPGA loading - an undef in the code made this
CONFIG_ useless.Signed-off-by: Stefano Babic
01 Aug, 2011
1 commit
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Fix compiler warning:
cmd_fpga.c:318: warning: passing argument 3 of 'fit_image_get_data'
from incompatible pointer typeAdding the needed 'const' here entails a whole bunch of additonal
changes all over the FPGA code.Signed-off-by: Wolfgang Denk
Cc: Andre Schwarz
Cc: Murray Jensen
Acked-by: Andre Schwarz
01 Dec, 2010
1 commit
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Currently the hardware was left in an undefined state in case Spartan3
serial load failed. This patch adds Xilinx_abort_fn to give the board
a possibility to clean up in this case.Signed-off-by: Wolfgang Wegner
25 Mar, 2010
1 commit
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Using seperate function calls for each bit-bang of slave serial
load can be painfully slow. This patch adds the possibility to
supply a block write function that loads the complete block of
data in one call (like it can already be done with Altera FPGAs).
On an MCF5373L (240 MHz) loading an XC3S4000 this reduces the load
time from around 15 seconds to around 3 secondsSigned-off-by: Wolfgang Wegner
03 Oct, 2009
1 commit
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PPC boards are the only users of the current FPGA code which is littered
with manual relocation fixups. Now that proper relocation is supported
for PPC boards, remove FPGA manual relocation.Signed-off-by: Peter Tyser
22 Feb, 2009
1 commit
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This patch does some minor fixing of the Xilinx Spartan III
FPGA boot code:- Fixed call order of post configuration callback and
success message printing (result of copy-paste?)
- remove obsolete comment
- minor coding style cleanupSigned-off-by: Matthias Fuchs
06 Dec, 2008
1 commit
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Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD
