10 Jan, 2014
4 commits
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Bringing in the MMC tree means that CONFIG_BOUNCE_BUFFER needed to be
added to include/configs/exynos5-dt.h now.Conflicts:
include/configs/exynos5250-dt.hSigned-off-by: Tom Rini
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This patch adds initial dts support for supported
zynq boards.Signed-off-by: Jagannadha Sutradharudu Teki
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This patch provides a basic fdt support for zynq u-boot.
zynq-7000.dtsi-> initial arch dts file
zynq-zed.dts -> initial zed board dts file
more devices should be added in subsequent patches.u-boot build: once configuring of a board done
for building dtb with zynq-zed.dts as an input
zynq-uboot> make DEVICE_TREE=zynq-zedEnabled CONFIG_OF_SEPARATE for building dtb separately.
There is a new binary called u-boot-dtb.bin which is a u-boot
with devicetree supported.Signed-off-by: Jagannadha Sutradharudu Teki
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Added support to find the bootmodes by reading
slcr bootmode register. this can be helpful to
autoboot the configurations w.r.t a specified bootmode.Added this functionality on board_late_init as it's not
needed for normal initializtion part.Signed-off-by: Jagannadha Sutradharudu Teki
09 Jan, 2014
1 commit
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Signed-off-by: David Feng
Signed-off-by: Bhupesh Sharma
08 Jan, 2014
2 commits
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Byte offset of Ethernet mac address read from e-fuse are wrong so DHCP is
not working on some boards, modifying the offset to read properly.Signed-off-by: Mugunthan V N
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The omap3_zoom2 board has not been updated for a correct CONFIG_SYS_HZ
and Tom Rix's email has long been bouncing.Signed-off-by: Tom Rini
07 Jan, 2014
1 commit
06 Jan, 2014
2 commits
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Conflicts:
include/micrel.hThe conflict above was trivial, caused by four lines being
added in both branches with different whitepace.
03 Jan, 2014
4 commits
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Define QIXIS_RST_FORCE_MEM to reset on-board DDR-DIMM before start
accessing it.Signed-off-by: Prabhakar Kushwaha
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The BOOT_LOC setting in rcw cfg is wrong, set it to Memory complex 1.
Signed-off-by: Shaohui Xie
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CONFIG_SPL_NAND_MINIMAL should not be used as it was defined for temporary
review purpose.So, use CONFIG_SPL_NAND_BOOT config.
Signed-off-by: Prabhakar Kushwaha
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T1040QDS has 256KB SRAM. Comment is showing wrong information.
So update the comment.
Signed-off-by: Prabhakar Kushwaha
31 Dec, 2013
1 commit
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This fix is necessary after increased by one the number
of adapters in s3c24x0 driver.Tested on Trats and Trats2.
Signed-off-by: Piotr Wilczek
Signed-off-by: Kyungmin Park
Cc: Minkyu Kang
Cc: Lukasz Majewski
Signed-off-by: Minkyu Kang
30 Dec, 2013
3 commits
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This patch adds dts support for SMDK5420.
exynos5.dtsi created is a common file which has the nodes common
to both 5420 and 5250.Signed-off-by: Akshay Saraswat
Signed-off-by: Rajeshwari S Shinde
Acked-by: Simon Glass
Signed-off-by: Minkyu Kang -
Adding the base patch for Exynos based SMDK5420.
This shall enable compilation and basic boot support for
SMDK5420.Signed-off-by: Rajeshwari S Shinde
Signed-off-by: Akshay Saraswat
Acked-by: Simon Glass
Signed-off-by: Minkyu Kang -
Create a common board.c file for all functions which are common across
all EXYNOS5 platforms.exynos_init function is provided for platform specific code.
Signed-off-by: Rajeshwari S Shinde
Acked-by: Simon Glass
Signed-off-by: Minkyu Kang
21 Dec, 2013
1 commit
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With changes to the rtl8169 ethernet to improve cache support, we have
needed additional cache functions for mpc8245. As the board maintainer
has been unresponsive, remove this board.Cc: Guennadi Liakhovetski
Signed-off-by: Tom Rini
19 Dec, 2013
14 commits
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GP EVM has 1GB DDR3 attached(Part no: MT41K512M8RH).
Adding details for the same.
Below is the brief description of DDR3 init sequence(SW leveling):
-> Enable VTT regulator
-> Configure VTP
-> Configure DDR IO settings
-> Disable initialization and refreshes until EMIF registers are programmed.
-> Program Timing registers
-> Program leveling registers
-> Program PHY control and Temp alert and ZQ config registers.
-> Enable initialization and refreshes and configure SDRAM CONFIG registerSigned-off-by: Lokesh Vutla
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AM4372 EPOS EVM has 1GB LPDDR2(Part no: MT42L256M32D2LG-25 WT:A)
Adding LPDDR2 init sequence and register details for the same.
Below is the brief description of LPDDR2 init sequence:
-> Configure VTP
-> Configure DDR IO settings
-> Disable initialization and refreshes until EMIF registers are programmed.
-> Program Timing registers
-> Program PHY control and Temp alert and ZQ config registers.
-> Enable initialization and refreshes and configure SDRAM CONFIG register
-> Wait till initialization is complete and the configure MR registers.Signed-off-by: Lokesh Vutla
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Currently same value is programmed for all ioregs. This is not
the case for all SoC's like AM4372. So adding a structure for ioregs
and updating in all board files. And also return from config_cmd_ctrl()
and config_ddr_data() functions if data is not passed.Signed-off-by: Lokesh Vutla
[trini: Fixup dxr2, cm_t335, adapt pcm051 rev3]
Signed-off-by: Tom Rini -
Updating the Multiplier and Dividers value for all DPLLs.
Safest OPP is read from DEV ATTRIBUTE register. Accoring to the value
returned the MPU DPLL is locked.
At different OPPs follwoing are the MPU locked frequencies.
OPP50 300MHz
OPP100 600MHz
OPP120 720MHz
OPPTB 800MHz
OPPNT 1000MHz
According to the latest DM following is the OPP table dependencies:
VDD_CORE VDD_MPU
OPP50 OPP50
OPP50 OPP100
OPP100 OPP50
OPP100 OPP100
OPP100 OPP120
So at different OPPs of MPU it is safest to lock CORE at OPP_NOM.
Following are the DPLL locking frequencies at OPP NOM:
Core locks at 1000MHz
Per locks at 960MHz
LPDDR2 locks at 266MHz
DDR3 locks at 400MHzTouching AM33xx files also to get DPLL values specific to board but no
functionality difference.
Signed-off-by: Lokesh Vutla -
Updating the mux data for UART, adding data for i2c0 and mmc.
And also updating pad_signals structure.Signed-off-by: Lokesh Vutla
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CONFIG_ENV_VARS_UBOOT_CONFIG, CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG and
CONFIG_BOARD_LATE_INIT is already set. Adding support to detect the
board. These variables are used by findfdt.Signed-off-by: Sekhar Nori
Signed-off-by: Lokesh Vutla -
Add support for reading onboard EEPROM to enable
board detection.Signed-off-by: Sekhar Nori
Signed-off-by: Lokesh Vutla -
Use ti_armv7_common.h config file to inclde the common
configs.Signed-off-by: Lokesh Vutla
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Add support for the new Tamonten™ NG platform from Avionic Design.
Currently only I2C, MMC, USB and ethernet have been tested.Signed-off-by: Alban Bedel
Reviewed-by: Stephen Warren
Signed-off-by: Tom Warren -
When DT define aliases for etherner0 and ethernet1, U-Boot
automatically patched MAC addresses using ethaddr and eth1addr
environment variables respectively.Custom initialization is no longer needed.
Signed-off-by: Sergei Ianovich
CC: Marek Vasut -
Signed-off-by: Sergei Ianovich
CC: Marek Vasut
18 Dec, 2013
7 commits
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The SH7753 EVB board has SH7753, 512MB DDR3-SDRAM, SPI ROM,
Gigabit Ethernet, and eMMC.This patch support the following functions:
- 512MB DDR3-SDRAM, SCIF4, SPI ROM, Gigabit Ethernet, eMMCSigned-off-by: Yoshihiro Shimoda
Signed-off-by: Nobuhiro Iwamatsu -
Signed-off-by: Nobuhiro Iwamatsu
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The koelsch board has one sh-ether device.
This supports sh-ether.Signed-off-by: Nobuhiro Iwamatsu
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The lager board uses I2C for reset.
ned-off-by: Nobuhiro Iwamatsu
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The lager board has one sh-ether device.
This supports sh-ether.Signed-off-by: Nobuhiro Iwamatsu
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mx6sabresd boards have a 18-bit LVDS data width and the correct color format
is RGB666.Suggested-by: Liu Ying
Signed-off-by: Fabio Estevam -
HSYNC, VSYNC and DISP_CLK are very useful display signals for debugging.
Configure them as active pins.
Signed-off-by: Fabio Estevam
