26 Nov, 2013
2 commits
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Fix ccsr_ddr structure to avoid using typedef. Combine DDR2 and DDR3
structure for 83xx, 85xx and 86xx.Signed-off-by: York Sun
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Freescale DDR driver has been used for mpc83xx, mpc85xx, mpc86xx SoCs.
The similar DDR controllers will be used for ARM-based SoCs.Signed-off-by: York Sun
01 Nov, 2013
1 commit
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Signed-off-by: Masahiro Yamada
Cc: Wolfgang Denk
Cc: Kim Phillips
Cc: York Sun
Cc: Stefan Roese
15 Oct, 2013
1 commit
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Signed-off-by: Wolfgang Denk
24 Jul, 2013
1 commit
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Signed-off-by: Wolfgang Denk
[trini: Fixup common/cmd_io.c]
Signed-off-by: Tom Rini
28 Nov, 2012
1 commit
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There were a number of shared files that were using
CONFIG_SYS_MPC85xx_DDR_ADDR, or CONFIG_SYS_MPC86xx_DDR_ADDR, and
several variants (DDR2, DDR3). A recent patchset added
85xx-specific ones to code which was used by 86xx systems.
After reviewing places where these constants were used, and
noting that the type definitions of the pointers assigned to
point to those addresses were the same, the cleanest approach
to fixing this problem was to unify the namespace for the
85xx, 83xx, and 86xx DDR address definitions.This patch does:
s/CONFIG_SYS_MPC8.xx_DDR/CONFIG_SYS_MPC8xxx_DDR/g
All 85xx, 86xx, and 83xx have been built with this change.
Signed-off-by: Andy Fleming
Tested-by: Andy Fleming
Acked-by: Kim Phillips
05 Nov, 2012
1 commit
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fsl_corenet_serdes.c:485:6: warning: symbol '__soc_serdes_init' was not declared. Should it be static?
cpu_init.c:185:6: warning: symbol 'invalidate_cpc' was not declared. Should it be static?
bcsr.c:28:27: warning: non-ANSI function declaration of function 'enable_8568mds_duart'
bcsr.c:39:33: warning: non-ANSI function declaration of function 'enable_8568mds_flash_write'
bcsr.c:46:34: warning: non-ANSI function declaration of function 'disable_8568mds_flash_write'
bcsr.c:53:29: warning: non-ANSI function declaration of function 'enable_8568mds_qe_mdio'
bcsr.c:28:33: warning: non-ANSI function declaration of function 'enable_8569mds_flash_write'
bcsr.c:33:34: warning: non-ANSI function declaration of function 'disable_8569mds_flash_write'
bcsr.c:38:28: warning: non-ANSI function declaration of function 'enable_8569mds_qe_uec'
bcsr.c:63:47: warning: non-ANSI function declaration of function 'disable_8569mds_brd_eeprom_write_protect'
ngpixis.c:245:1: error: directive in argument list
ngpixis.c:247:1: error: directive in argument listSigned-off-by: Kim Phillips
29 Jul, 2012
1 commit
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Also drop a few files referring to no longer / not yet supported
boards.Signed-off-by: Wolfgang Denk
Cc: Prafulla Wadaskar
Cc: Stefan Roese
Cc: Kim Phillips
Cc: Andy Fleming
Cc: Jason Jin
Cc: Stefano Babic
Cc: Daniel Schwierzeck
Acked-by: Stefano Babic
Acked-by: Daniel Schwierzeck
11 Nov, 2011
1 commit
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mpc8569mds.c: In function 'local_bus_init':
mpc8569mds.c:306:7: warning: variable 'lbc_hz' set but not used [-Wunused-but-set-variable]Signed-off-by: Kumar Gala
16 Oct, 2011
1 commit
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The top level Makefile does not do any recursion into subdirs when
cleaning, so these clean/distclean targets in random arch/board dirs
never get used. Punt them all.MAKEALL didn't report any errors related to this that I could see.
Signed-off-by: Mike Frysinger
21 Apr, 2011
1 commit
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The fsl_phy_enet_if enum was, essentially, the phy_interface_t enum.
This meant that drivers which used fsl_phy_enet_if to deal with
PHY interfaces would have to convert between the two (or we would have
to have them mirror each other, and deal with the ensuing maintenance
headache). Instead, we switch all clients of fsl_phy_enet_if over to
phy_interface_t, which should become the standard, anyway.Signed-off-by: Andy Fleming
Acked-by: Detlev Zundel
04 Apr, 2011
3 commits
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Move fsl_ddr_get_spd into common mpc8xxx/ddr/main.c as most boards
pretty much do the same thing. The only variations are in how many
controllers or DIMMs per controller exist. To make this work we
standardize on the names of the SPD_EEPROM_ADDRESS defines based on the
use case of the board.We allow boards to override get_spd to either do board specific fixups
to the SPD data or deal with any unique behavior of how the SPD eeproms
are wired up.Signed-off-by: Kumar Gala
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Every 85xx board implements fsl_ddr_get_mem_data_rate via get_ddr_freq()
and every 86xx board uses get_bus_freq(). If implement get_ddr_freq()
as a static inline to call get_bus_freq() we can remove
fsl_ddr_get_mem_data_rate altogether and just call get_ddr_freq()
directly.Signed-off-by: Kumar Gala
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Move the include of mpc85xx/u-boot-nand.lds to utilize
CONFIG_SYS_LDSCRIPT rather than having an explicit config.mkSigned-off-by: Kumar Gala
14 Jan, 2011
4 commits
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Signed-off-by: Kumar Gala
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Remove duplicated code in MPC8569MDS board and utilize the common
fsl_pcie_init_board(). We also now dynamically setup the LAWs for PCI
controllers based on which PCIe controllers are enabled.Signed-off-by: Kumar Gala
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Correct initdram to use phys_size_t to represent the size of
dram; instead of changing this all over the place, and correcting
all the other random errors I've noticed, create a
common initdram that is used by all non-corenet 85xx parts. Most
of the initdram() functions were identical, with 2 common differences:1) DDR tlbs for the fixed_sdram case were set up in initdram() on
some boards, and were part of the tlb_table on others. I have
changed them all over to the initdram() method - we shouldn't
be accessing dram before this point so they don't need to be
done sooner, and this seems cleaner.2) Parts that require the DDR11 erratum workaround had different
implementations - I have adopted the version from the Freescale
errata document. It also looks like some of the versions were
buggy, and, depending on timing, could have resulted in the
DDR controller being disabled. This seems bad.The xpedite boards had a common/fsl_8xxx_ddr.c; with this
change only the 517 board uses this so I have moved the ddr code
into that board's directory in xpedite517x.cSigned-off-by: Becky Bruce
Tested-by: Paul Gortmaker
Signed-off-by: Kumar Gala -
Now that we have serdes support for all 85xx/86xx/Pxxx chips we can
replace the is_fsl_pci_cfg() code with the is_serdes_configured().Signed-off-by: Kumar Gala
18 Nov, 2010
1 commit
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Before this commit, weak symbols were not overridden by non-weak symbols
found in archive libraries when linking with recent versions of
binutils. As stated in the System V ABI, "the link editor does not
extract archive members to resolve undefined weak symbols".This commit changes all Makefiles to use partial linking (ld -r) instead
of creating library archives, which forces all symbols to participate in
linking, allowing non-weak symbols to override weak symbols as intended.
This approach is also used by Linux, from which the gmake function
cmd_link_o_target (defined in config.mk and used in all Makefiles) is
inspired.The name of each former library archive is preserved except for
extensions which change from ".a" to ".o". This commit updates
references accordingly where needed, in particular in some linker
scripts.This commit reveals board configurations that exclude some features but
include source files that depend these disabled features in the build,
resulting in undefined symbols. Known such cases include:
- disabling CMD_NET but not CMD_NFS;
- enabling CONFIG_OF_LIBFDT but not CONFIG_QE.Signed-off-by: Sebastien Carlier
15 Nov, 2010
1 commit
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Previously boards used a variety of indentations, newline styles, and
colon styles for the PCI information that is printed on bootup. This
patch unifies the style to look like:...
NAND: 1024 MiB
PCIE1: connected as Root Complex
Scanning PCI bus 01
04 01 8086 1010 0200 00
04 01 8086 1010 0200 00
03 00 10b5 8112 0604 00
02 01 10b5 8518 0604 00
02 02 10b5 8518 0604 00
08 00 1957 0040 0b20 00
07 00 10b5 8518 0604 00
09 00 10b5 8112 0604 00
07 01 10b5 8518 0604 00
07 02 10b5 8518 0604 00
06 00 10b5 8518 0604 00
02 03 10b5 8518 0604 00
01 00 10b5 8518 0604 00
PCIE1: Bus 00 - 0b
PCIE2: connected as Root Complex
Scanning PCI bus 0d
0d 00 1957 0040 0b20 00
PCIE2: Bus 0c - 0d
In: serial
...Signed-off-by: Peter Tyser
CC: wd@denx.de
CC: sr@denx.de
CC: galak@kernel.crashing.org
20 Oct, 2010
1 commit
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Add a common helper that will set the PHY connection type based on enum.
We use this on eTSEC, UCC, and will with Fman in the future.Signed-off-by: Kumar Gala
19 Oct, 2010
3 commits
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Clean up Makefile, and drop a lot of the config.mk files on the way.
We now also automatically pick all boards that are listed in
boards.cfg (and with all configurations), so we can drop the redundant
entries from MAKEALL to avoid building these twice.Signed-off-by: Wolfgang Denk
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The change is currently needed to be able to remove the board
configuration scripting from the top level Makefile and replace it by
a simple, table driven script.Moving this configuration setting into the "CONFIG_*" name space is
also desirable because it is needed if we ever should move forward to
a Kconfig driven configuration system.Signed-off-by: Wolfgang Denk
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When planning for more generalization and Makefile cleanup it became
obvious that the introduction of a separate CONFIG_MK_ name space for
config options that were set through scripting in the Makefile was
not a good idea.Originally the idea was to provide a script-free approach to supply
configuration options - there was no real need for a separate name
space. But when we now convert the existing Makefile entries to make
use of this approach, it would mean that we have to touch a large
number of board config files and add #ifdef / #define sequences to
"convert" from the CONFIG_MK_ to the CONFIG_ name space.It seems much cleaner to get rid of this somewhat arbitrary _MK
string now for the few boards that actually use it.Signed-off-by: Wolfgang Denk
Acked-by: Mike Frysinger
07 Oct, 2010
2 commits
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Enable half drive strength, set RTT to 60Ohm and set write leveling override.
Signed-off-by: Haiying Wang
Signed-off-by: Kumar Gala -
The original code maps boot flash as non-cacheable region. When calling
relocate_code in flash to copy u-boot from flash to ddr, every loop copy command
is read from flash. The flash read speed will be the bottleneck, which consuming
long time to do this operation. To resovle this, map the boot flash as
write-through cache via tlb. And set tlb to remap the flash after code
executing in ddr, to confirm flash erase operation properly done.Signed-off-by: Kai.Jiang
Signed-off-by: Kumar Gala
20 Jul, 2010
1 commit
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Previously we used an alias the pci node to determine which node to
fixup or delete. Now we use the new fdt_node_offset_by_compat_reg to
find the node to update.Additionally, we replace the code in each board with a single macro call
that makes assumes uniform naming and reduces duplication in this area.Signed-off-by: Kumar Gala
16 Jul, 2010
1 commit
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Currently, 83xx, 86xx, and 85xx have a lot of duplicated code
dedicated to defining and manipulating the LBC registers. Merge
this into a single spot.To do this, we have to decide on a common name for the data structure
that holds the lbc registers - it will now be known as fsl_lbc_t, and we
adopt a common name for the immap layouts that include the lbc - this was
previously known as either im_lbc or lbus; use the former.In addition, create accessors for the BR/OR regs that use in/out_be32
and use those instead of the mismash of access methods currently in play.I have done a successful ppc build all and tested a board or two from
each processor family.Signed-off-by: Becky Bruce
Acked-by: Kim Phillips
Signed-off-by: Kumar Gala
13 Apr, 2010
1 commit
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The CPUDIR variable points to the location of a target's CPU directory.
Currently, it is set to cpu/$CPU. However, using $CPUDIR will allow for
more flexibility in the future. It lays the groundwork for reorganizing
U-Boot's directory structure to support a layout such as:arch/$ARCH/cpu/$CPU/* (architecture with multiple CPU types)
arch/$ARCH/cpu/* (architecture with one CPU type)Signed-off-by: Peter Tyser
28 Jan, 2010
1 commit
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This patch add nand boot support for MPC8569mds board.
Signed-off-by: Liu Yu
26 Jan, 2010
1 commit
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Signed-off-by: Liu Yu
Signed-off-by: Kumar Gala
18 Jan, 2010
1 commit
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When referring to PCIe and USB 'endpoint' is the standard naming
convention.Signed-off-by: Peter Tyser
Acked-by: Stefan Roese
Acked-by: Remy Bohmer
06 Jan, 2010
2 commits
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Thanks to "Errata to MPC8569E PowerQUICC III Integrated Host Processor
Family Reference Manual, Rev. 0" document, which describes all eSDHC
pins, we can add 4-bits eSDHC support for MPC8569E-MDS boards.Signed-off-by: Anton Vorontsov
Signed-off-by: Kumar Gala -
Use new fsl_pci_init_port() that reduces amount of duplicated code in the
board ports, use IO accessors and clean up printing of status info.Signed-off-by: Kumar Gala
27 Oct, 2009
6 commits
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Setup QE pin multiplexing for USB function, configure needed BCSRs
and add some fdt fixups.Signed-off-by: Anton Vorontsov
Signed-off-by: Kumar Gala -
To make QE UART usable by Linux we should setup pin multiplexing
and turn UCC2 Ethernet node into UCC2 QE UART node.Also, QE UART is mutually exclusive with UART0, so we can't enable
it if eSDHC is in 4-bits mode on pilot boards, or if it's a prototype
board with eSDHC in 1- or 4-bits mode.Signed-off-by: Anton Vorontsov
Signed-off-by: Kumar Gala -
SPI Flash (M25P40) is connected to the SPI1 bus, we need a few
qe_iop entries to actually enable SPI1 on these boards.Signed-off-by: Anton Vorontsov
Signed-off-by: Kumar Gala -
This patch sets memory window for Serial RapidIO on MPC8569E-MDS
boards.Signed-off-by: Anton Vorontsov
Signed-off-by: Kumar Gala -
Simply add some defines, and adjust TLBe setup to include some
space for eLBC NAND.Signed-off-by: Anton Vorontsov
Signed-off-by: Kumar Gala -
eSDHC is mutually exlusive with UART0 (in 4-bits mode) and I2C2
(in 1-bit mode). When eSDHC is used, we should switch u-boot console to
UART1, and make the proper device-tree fixups.Because of an erratum in prototype boards it is impossible to use eSDHC
without disabling UART0 (which makes it quite easy to 'brick' the board
by simply issung 'setenv hwconfig esdhc', and not able to interact with
U-Boot anylonger).So, but default we assume that the board is a prototype, which is a most
safe assumption. There is no way to determine board revision from a
register, so we use hwconfig.Signed-off-by: Anton Vorontsov
Signed-off-by: Kumar Gala