26 Feb, 2014
1 commit
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With this, fixup a trivial build error of get_effective_memsize needing
to be updated in the new board/freescale/p1010rdb/spl.cSigned-off-by: Tom Rini
25 Feb, 2014
1 commit
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In the previous patches, we introduced the SPL/TPL fraamework.
For SD/SPI flash booting way, we introduce the SPL to enable a loader stub. The
SPL was loaded by the code from the internal on-chip ROM. The SPL initializes
the DDR according to the SPD and loads the final uboot image into DDR, then
jump to the DDR to begin execution.For NAND booting way, the nand SPL has size limitation on some board(e.g.
P1010RDB), it can not be more than 8KB, we can call it "minimal SPL", So the
dynamic DDR driver doesn't fit into this minimum SPL. We added the TPL that is
loaded by the the minimal SPL. The TPL initializes the DDR according to the SPD
and loads the final uboot image into DDR,then jump to the DDR to begin execution.This patch enabled SPL/TPL for P1010RDB to support starting from NAND/SD/SPI
flash with SPL framework and initializing the DDR according to SPD in the SPL/TPL.
Because the minimal SPL load the TPL to L2 SRAM and the jump to the L2 SRAM to
execute, so the section .resetvec is no longer needed.Signed-off-by: Ying Zhang
Reviewed-by: York Sun
22 Jan, 2014
1 commit
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u-boot binary size for Freescale mpc85xx platforms is 512KB.
This has been reached to upper limit for some of the platforms causig
linker error.So, Increase the u-boot binary size to 768KB.
Signed-off-by: York Sun
Signed-off-by: Prabhakar Kushwaha
03 Jan, 2014
1 commit
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CONFIG_SPL_NAND_MINIMAL should not be used as it was defined for temporary
review purpose.So, use CONFIG_SPL_NAND_BOOT config.
Signed-off-by: Prabhakar Kushwaha
26 Nov, 2013
3 commits
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Freescale IFC controller has been used for mpc8xxx. It will be used
for ARM-based SoC as well. This patch moves the driver to driver/misc
and fix the header file includes.Signed-off-by: York Sun
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Fix ccsr_ddr structure to avoid using typedef. Combine DDR2 and DDR3
structure for 83xx, 85xx and 86xx.Signed-off-by: York Sun
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Freescale DDR driver has been used for mpc83xx, mpc85xx, mpc86xx SoCs.
The similar DDR controllers will be used for ARM-based SoCs.Signed-off-by: York Sun
14 Nov, 2013
1 commit
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- Remove duplicate doc/README.p1010rdb
- Rename README to README.P1010RDB-PA
- Add new README.P1010RDB-PBP1010RDB-PB is a variation of previous P1010RDB-PA board.
Signed-off-by: Shengzhou Liu
01 Nov, 2013
1 commit
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Signed-off-by: Masahiro Yamada
Cc: Wolfgang Denk
Cc: Kim Phillips
Cc: York Sun
Cc: Stefan Roese
17 Oct, 2013
4 commits
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- Rename old P1010RDB board as P1010RDB-PA.
- Add support for new P1010RDB-PB board.
- Some optimization.For more details, see board/freescale/p1010rdb/README.
Signed-off-by: Shengzhou Liu
[York Sun: fix conflicts in boards.cfg]
Acked-by: York Sun -
Since pins multiplexing, SDHC shares signals with IFC, with this patch:
To enable SDHC in case of NOR/NAND/SPI boot
a) For temporary use case in runtime without reboot system
run 'mux sdhc' in u-boot to validate SDHC with invalidating IFC.
b) For long-term use case
set 'esdhc' in hwconfig and save it.
To enable IFC in case of SD boot
a) For temporary use case in runtime without reboot system
run 'mux ifc' in u-boot to validate IFC with invalidating SDHC.
b) For long-term use case
set 'ifc' in hwconfig and save it.Signed-off-by: Shengzhou Liu
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Function cpld_show() was for debug and not called, so clean it.
Signed-off-by: Shengzhou Liu
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Some DDR related structures present in fsl_ddr_dimm_params.h, fsl_ddr_sdram.h, ddr_spd.h
has various parameters with embedded acronyms capitalized that trigger the CamelCase
warning in checkpatch.plConvert those variable names to smallcase naming convention and modify all files
which are using these structures with modified structures.Signed-off-by: Priyanka Jain
21 Aug, 2013
1 commit
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There was a bug for calculating ddr_freq_mhz,
it should be divided by 1000000 rather than 0x1000000.Signed-off-by: Shengzhou Liu
Acked-by: York Sun
10 Aug, 2013
1 commit
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JEDEC spec requires the clocks to be stable before deasserting reset
signal for RDIMMs. Clocks start when any chip select is enabled and
clock control register is set. This patch also adds the interface to
toggle memory reset signal if needed by the boards.Signed-off-by: York Sun
24 Jul, 2013
1 commit
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Signed-off-by: Wolfgang Denk
[trini: Fixup common/cmd_io.c]
Signed-off-by: Tom Rini
21 Jun, 2013
3 commits
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PCIe TLB should be created with CONFIG_PCI defined
Signed-off-by: Prabhakar Kushwaha
Signed-off-by: Andy Fleming -
e500v2 processor does not support 8K page size TLB entries.
So create new TLB entry only during NAND SPL boot.
Signed-off-by: Prabhakar Kushwaha
Signed-off-by: Andy Fleming -
- defines constants
- Add spl_minimal.c to initialise DDR
- update TLB entries as per NAND boot
- remove nand_spl support for P1010RDBSigned-off-by: Prabhakar Kushwaha
Signed-off-by: Andy Fleming
03 May, 2013
1 commit
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Change flexcan compatible string from "fsl,flexcan-v1.0"
to "fsl,p1010-flexcan" to match the device tree.Signed-off-by: Shengzhou Liu
Signed-off-by: Andy Fleming
04 Feb, 2013
1 commit
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Move these fields into arch_global_data and tidy up.
Signed-off-by: Simon Glass
[trini: Update for bsc9132qds.c, b4860qds.c]
Signed-off-by: Tom Rini
23 Aug, 2012
1 commit
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There was an extra 0 in front of the value we were using to mask,
remove it to improve the code.Also fix the value written to ddr_sdram_cfg to set the bus width
properly to 16 bitsSigned-off-by: Matthew McClintock
Signed-off-by: Andy Fleming
23 Jul, 2012
1 commit
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Signed-off-by: Wolfgang Denk
10 Jul, 2012
1 commit
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Signed-off-by: Wolfgang Denk
07 Jul, 2012
3 commits
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We don't care E bit of SVR in most cases. Clear E bit for SVR_SOC_VER().
This will simplify the coding. Use IS_E_PROCESSOR() to identify SoC with
encryption. Remove all _E entries from SVR list and CPU list.Signed-off-by: York Sun
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Signed-off-by: Shengzhou Liu
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On p1010rdb some signals are muxed for tdm/can/uart/flash.
If we don't set fsl_p1010mux:tdm_can to "can" or "tdm" explicitly,
defaultly we keep spi chip selection to spi-flash instead of to
tdm/slic and disable uart1 when not using flexcan, as well disable sdhc.Signed-off-by: Shengzhou Liu
25 Apr, 2012
2 commits
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Most 85xx boards can be built as a 32-bit or a 36-bit. Current code sometimes
displays which of these is actually built, but it's inconsistent. This is
especially problematic since the "default" build for a given 85xx board can
be either one, so if you don't see a message, you can't always know which
size is being used. Not only that, but each board includes code that displays
the message, so there is duplication.The 'bdinfo' command has been updated to display this information, so
we don't need to display it at boot time. The board-specific code is
deleted.Signed-off-by: Timur Tabi
Signed-off-by: Andy Fleming -
P1010RDB and p1_pc_rdb_pc has incorrect configuration for
CONFIG_DDR_RAW_TIMING. It should be CONFIG_SYS_DDR_RAW_TIMING.
Incorrect setting causes DDR failure in case of SPD absent.Signed-off-by: York Sun
Signed-off-by: Andy Fleming
08 Nov, 2011
1 commit
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Include call to usb device-fixup only when CONFIG_HAS_FSL_DR_USB is
defined for the platform - P1020RDB, P1010RDB, P1020-PCSigned-off-by: Ramneek Mehresh
Signed-off-by: Kumar Gala
16 Oct, 2011
1 commit
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The top level Makefile does not do any recursion into subdirs when
cleaning, so these clean/distclean targets in random arch/board dirs
never get used. Punt them all.MAKEALL didn't report any errors related to this that I could see.
Signed-off-by: Mike Frysinger
30 Sep, 2011
1 commit
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Boot methods supported: NOR Flash, SPI Flash and SDCARD
This patch adds the following basic interfaces:
DDR3, eTSEC, DUART, I2C, SD/MMC, USB, SATA, PCIe, NOR Flash, SPI Flash.P1010RDB Overview
-----------------
1Gbyte DDR3 (on board DDR)
Local Bus (IFC):
32Mbyte 16bit NOR flash
32Mbyte SLC NAND Flash
64KB CPLD device(GPCM interface)
SPI Flash:
128 Mbit SPI Flash memory
SD/MMC:
connector to interface with the SD memory card
SATA:
1 internal SATA connect to 2.5. 160G SATA2 HDD
1 eSATA connector to rear panel
USB 2.0:
x1 USB 2.0 port: connected via a UTMI PHY to Mini-AB interface.
x1 USB 2.0 port: directly connected to Mini-AB interface Ethernet
eTSEC:
eTSEC1: Connected to RGMII PHY VSC8641XKO
eTSEC2: Connected to SGMII PHY VSC8221
eTSEC3: Connected to SGMII PHY VSC8221
eCAN:
Two DB-9 female connectors for Field bus interface
UART:
supports two UARTs up to 115200 bps for console
TDM:
2 FXS ports connected via an external SLIC to the TDM interface.
SLIC:
SPI SLIC
I2C:
Serial EEprom
Real time clock
256 Kbit M24256 I2C EEPROM
PCIe:
PCIe and mPCIe connectors.Signed-off-by: Poonam Aggrwal
Signed-off-by: Dipen Dudhat
Signed-off-by: Prabhakar Kushwaha
Signed-off-by: Ramneek Mehresh
Signed-off-by: Bhaskar Upadhaya
Signed-off-by: York Sun
Signed-off-by: Kumar Gala
