12 Jul, 2014
1 commit
10 Jul, 2014
2 commits
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The pad settings for DISP0_DATA02 and DISP0_DAT10 were not
set in the same way as DISP0_DAT00-23, causing much flicker
in parallel RGB displays on Dual-Lite and Solo processors.These settings now match the i.MX6 Dual and Quad core versions.
Note that this fixes a regression in commit b47abc3 and that
this is the second time we've had a regression on these two
pads (See commit e654ddf).Signed-off-by: Eric Nelson
Acked-by: Otavio Salvador -
Newer AM437x silicon requires us to explicitly power up
the USB2 PHY. By implementing usb_phy_power() we can
achieve that.Signed-off-by: Felipe Balbi
09 Jul, 2014
3 commits
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Commit 3d622b78 (mx6: soc: Introduce set_ldo_voltage()) introduces
set_ldo_voltage() function that can be used to set the voltages
of any of the three LDO regulators controlled by the PMU_REG_CORE register.Prior to this commit there was a single set_vddsoc() which only configured the
VDDSOC regulator.Update the comments to align with the new set_ldo_voltage() implementation.
Signed-off-by: Fabio Estevam
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DIV_SELECT is used as Fout = Fin * div_select / 2.0, so we should do
the shift after the multiply to avoid rounding errorsSigned-off-by: Andre Renaud
08 Jul, 2014
14 commits
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Fixes a bug when objcopy doesn't put .dtb.init.rodata section to resulting
u-boot.bin, so u-boot was unable to find embedded DTB. -
Since ARRAY_SIZE macro is defined in include/common.h,
re-defining it in arch-specific files is redundant.Signed-off-by: Masahiro Yamada
Acked-by: Stefan Roese
Acked-by: Sonic Zhang -
Add invalidate_dcache_range() and flush_dcache_range() for the blackfin
architecture. Such functions already exist on this arch with different
names, so just forward the call.This fixes the build of bf609-ezkit board as it uses
drivers/net/designware.c which requires the above functions.Cc: Sonic Zhang , Alexey Brodkin
Signed-off-by: Vasili Galka -
The csarX and cscrX registers in the fbcs_t struct are 16-bit for
CONFIG_M5235 and 32-bit wide otherwise. The code in cpu_init.c
accessed them always as 32-bit, effectively creating a wrong memory
access on M5235. Fixed that by choosing out_be16/out_be32 depending
on whether CONFIG_M5235 is defined or not.Cc: Jason Jin
Signed-off-by: Vasili Galka -
in_be16() shall be passed a pointer to register and not its value. This
is clearly a typo resulting in a wrong memory access, so fix it.Cc: Alison Wang , Jason Jin
Signed-off-by: Vasili Galka -
This board is old enough and has no maintainer.
Signed-off-by: Masahiro Yamada
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These boards are old enough and have no maintainers.
Signed-off-by: Masahiro Yamada
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These boards are old enough and have no maintainers.
Signed-off-by: Masahiro Yamada
-
These boards are old enough and have no maintainers.
Signed-off-by: Masahiro Yamada
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These boards are old enough and have no maintainers.
Signed-off-by: Masahiro Yamada
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* This is done by limiting the ARM's bandwidth and setting DSS priority in
the EMIF controller to ensure underflows do not occur. -
* Boot failures have been discovered due to a combination of routing issues and
non optimal ddr3 timings in the EMIF
* Since ddr3 timings are different after significant board layout changes
different timings are required for alpha, beta and production boards.Signed-off-by: Franklin S. Cooper Jr
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The directory arch/${ARCH}/cpu/${CPU} does not exist
in avr32, blackfin, microblaze, nios2, openrisc, sandbox, x86.These architectures have only one CPU type.
Defining CPU should not be required for such architectures.This commit allows cpu field (= the 3rd field of boards.cfg)
to be kept blank.Signed-off-by: Masahiro Yamada
Cc: Andreas Bießmann
Cc: Simon Glass
Cc: Sonic Zhang
Cc: Michal Simek
Cc: Thomas Chou
Cc: Stefan Kristiansson -
The code intends for the CM_DLL_READYST to be set, but
actually polls till any bit is set since the logical
AND is used instead of the bitwise one is used. Fix it.cc: Lokesh Vutla
Signed-off-by: Jeroen Hofstee
07 Jul, 2014
1 commit
05 Jul, 2014
8 commits
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To move the arch common function away from board folder to
arch/arm/cpu/armv7/socfpga folder. Its to avoid code duplication
for other non Altera dev kit which is using socfpga device.Signed-off-by: Chin Liang See
Cc: Wolfgang Denk
Cc: Detlev Zundel
Cc: Pavel Machek
Cc: Dinh Nguyen
Acked-by: Detlev Zundel -
Fix following compilation error when CONFIG_ARM64 is defined
Error: unknown or missing system register name at operand 2
-- `mrs x0,daifmsr daifset,#3'Signed-off-by: Shaibal.Dutta
Signed-off-by: Darwin Rambo
Reviewed-by: Darwin Rambo -
cc: Tom Rini
Signed-off-by: Jeroen Hofstee -
Scan Manager driver will be called to configure the IOCSR
scan chain. This configuration will setup the IO buffer settingsSigned-off-by: Chin Liang See
Cc: Dinh Nguyen
Cc: Wolfgang Denk
CC: Pavel Machek
Cc: Tom Rini
Cc: Albert Aribaud -
To enable the DesignWare watchdog support at SOCFPGA
Cyclone V dev kit.Signed-off-by: Chin Liang See
Cc: Anatolij Gustschin
Cc: Albert Aribaud
Cc: Heiko Schocher
Cc: Tom Rini -
This patch returns back support for old ep93xx processors family
Signed-off-by: Sergey Kostanbaev
Cc: albert.u.boot@aribaud.net -
This is not only more readable but also prevents a warning
about a missing prototype. The prototypes which are actually
missing are added.cc: Albert Aribaud
Signed-off-by: Jeroen Hofstee
Reviewed-by: Tom Rini -
LS2085A is an ARMv8 implementation. This adds board support for emulator
and simulator:
Two DDR controllers
UART2 is used as the console
IFC timing is tightened for speedy booting
Support DDR3 and DDR4 as separated targets
Management Complex (MC) is enabled
Support for GIC 500 (based on GICv3 arch)Signed-off-by: York Sun
Signed-off-by: Arnab Basu
Signed-off-by: J. German Rivera
Signed-off-by: Bhupesh Sharma
03 Jul, 2014
6 commits
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Adding support to load and start the Layerscape Management Complex (MC)
firmware. First, the MC GCR register is set to 0 to reset all cores. MC
firmware and DPL images are copied from their location in NOR flash to
DDR. MC registers are updated with the location of these images.
Deasserting the reset bit of MC GCR register releases core 0 to run.
Core 1 will be released by MC firmware. Stop bits are not touched for
this step. U-boot waits for MC until it boots up. In case of a failure,
device tree is updated accordingly. The MC firmware image uses FIT format.Signed-off-by: J. German Rivera
Signed-off-by: York Sun
Signed-off-by: Lijun Pan
Signed-off-by: Shruti Kanetkar -
Freescale LayerScape with Chassis Generation 3 is a set of SoCs with
ARMv8 cores and 3rd generation of Chassis. We use different MMU setup
to support memory map and cache attribute for these SoCs. MMU and cache
are enabled very early to bootst performance, especially for early
development on emulators. After u-boot relocates to DDR, a new MMU
table with QBMan cache access is created in DDR. SMMU pagesize is set
in SMMU_sACR register. Both DDR3 and DDR4 are supported.Signed-off-by: York Sun
Signed-off-by: Varun Sethi
Signed-off-by: Arnab Basu -
Make MMU function reusable. Platform code can setup its own MMU tables.
Signed-off-by: York Sun
CC: David Feng -
This is needed for accessing peripherals with 64-bit MMIO registers,
from ARMv8 processors.Signed-off-by: J. German Rivera
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The armv8 ARM Trusted Firmware (ATF) can be used to load various ATF
images and u-boot, and does this for virtual platforms by using
semihosting. This commit extends this idea by allowing u-boot to also
use semihosting to load the kernel/ramdisk/dtb. This eliminates the need
for a bootwrapper and produces a more realistic boot sequence with
virtual models.Though the semihosting code is quite generic, support for armv7 in
fastmodel is less useful due to the wide range of available silicon
and the lack of a free armv7 fastmodel, so this change contains an
untested armv7 placeholder for the service trap opcode.Please refer to doc/README.semihosting for a more detailed description
of semihosting and how it is used with the armv8 virtual platforms.Signed-off-by: Darwin Rambo
Cc: trini@ti.com
Cc: fenghua@phytium.com.cn
Cc: bhupesh.sharma@freescale.com -
I2C read transactions are typically implemented as follows:
START(write) address REPEATED_START(read) data... STOP
However, Tegra's I2C driver currently implements reads as follows:
START(write) address STOP START(read) data... STOP
This sequence confuses at least the AS3722 PMIC on the Jetson TK1 board,
leading to corrupted read data in some cases. Fix the driver to chain
the transactions together using repeated starts to solve this.Signed-off-by: Stephen Warren
Reviewed-by: Yen Lin
02 Jul, 2014
1 commit
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Conflicts:
boards.cfgConflict was trivial between goni maintainer change and
lager_nor removal.
01 Jul, 2014
3 commits
25 Jun, 2014
1 commit
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commit 67a04ab3ab8522a3a34491853e46105317580df5
fix the build for MX25. The same error
happens for VF610 SOC.Signed-off-by: Stefano Babic
