17 May, 2016
1 commit
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* 'master' of git://git.denx.de/u-boot: (31 commits)
Prepare v2016.05
sunxi: Enable USB host in CHIP defconfig
test, tools: update tbot documentation
tests: py: fix NameError exception if bdi cmd is not supported
arm/arm64: Move barrier instructions into separate header
arm: socfpga: Update iomux and pll for c5 socdk RevE
warp7: Fix boot by selecting CONFIG_OF_LIBFDT
usb: gadget: dfu: discard dead code
dfu: avoid memory leak
usb: dwc2: Add delay to fix the USB detection problem on SoCFPGA
usb: hub: Don't continue on get_port_status failure
usb: Assure Get Descriptor request is in separate microframe
usb: Wait after sending Set Configuration request
socfpga: fix broken build if CONFIG_ETH_DESIGNWARE disabled
mtd: cqspi: Simplify indirect read code
mtd: cqspi: Simplify indirect write code
arm: socfpga: socrates: Add 'time' command
ARM: socfpga: Disable USB OC protection on SoCrates
usb: Don't init pointer to zero, but NULL
usb: ehci-mx6: allow board_ehci_hcd_init to fail
...Signed-off-by: Lokesh Vutla
06 May, 2016
1 commit
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Spelling corrections for (among other things):
* environment
* override
* variable
* ftd (should be "fdt", for flattened device tree)
* embedded
* FTDI
* emulation
* controller
05 May, 2016
1 commit
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Signed-off-by: Lokesh Vutla
03 May, 2016
2 commits
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I'll switch my mails to my own server, so drop all gmail references.
Signed-off-by: Andreas Bießmann
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The getopt(3) optstring '-' is a GNU extension which is not available on BSD
systems like OS X.Remove this dependency by implementing argument parsing in another way. This
will also change the lately introduced '-b' switch behaviour.Signed-off-by: Andreas Bießmann
Reviewed-by: Simon Glass
26 Apr, 2016
1 commit
19 Apr, 2016
2 commits
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Add the device tree bindings and the accompanying documentation
for the TI DP83867 Giga bit ethernet phy driver.The original document was from:
[commit 2a10154abcb75ad0d7b6bfea6210ac743ec60897 from the Linux kernel]Signed-off-by: Dan Murphy
Signed-off-by: Mugunthan V N -
Clean up the ext4 README file.
Signed-off-by: Robert P. J. Day
18 Apr, 2016
1 commit
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Adds doc/README.ti-secure file to explain in generic terms
how boot images need to be created for secure devices from
Texas Instruments.Specific details for creating secure boot images for the
AM43xx, DRA7xx and AM57xx secure devices from Texas
Instruments are also provided in the README file.Secure devices require a security development package (SECDEV)
package that can be downloaded from:http://www.ti.com/mysecuresoftware
Login is required and access is granted under appropriate NDA
and export control restrictions.Signed-off-by: Madan Srinivas
Signed-off-by: Daniel Allred
15 Apr, 2016
1 commit
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Since all the tests are implemented in pytest infrastructure,
So update the dm tests with the same instead of ./test/dm/test-dm.shCc: Tom Rini
Cc: Simon Glass
Acked-by: Stephen Warren
Signed-off-by: Jagan Teki
14 Apr, 2016
2 commits
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The firmware from link [1] only works with U-Boot image that is no
bigger than 328KiB. Using it with the default mainline U-Boot today
which is already around 500KiB is just not working. Correct the link
to be hardkernel_1mb_uboot one [2], so that users can get mainline
U-Boot work out of box.While at it, the README is updated to include XU4 support, like DTB file
name.[1] https://github.com/hardkernel/u-boot/tree/odroidxu3-v2012.07/sd_fuse/hardkernel
[2] https://github.com/hardkernel/u-boot/tree/odroidxu3-v2012.07/sd_fuse/hardkernel_1mb_ubootSigned-off-by: Shawn Guo
Acked-by: Przemyslaw Marczak
Reviewed-by: Anand Moon
Signed-off-by: Minkyu Kang -
Signed-off-by: Moritz Fischer
Reviewed-by: Heiko Schocher
Signed-off-by: Michal Simek
07 Apr, 2016
1 commit
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LS2080A is the primary SoC, and LS2085A is a personality with AIOP
and DPAA DDR. The RDB and QDS boards support both personality. By
detecting the SVR at runtime, a single image per board can support
both SoCs. It gives users flexibility to swtich SoC without the need
to reprogram the board.Signed-off-by: York Sun
CC: Prabhakar Kushwaha
Reviewed-by: Prabhakar Kushwaha
02 Apr, 2016
12 commits
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- Update MAINTAINERS
- Update git-mailrcSigned-off-by: Mateusz Kulikowski
Reviewed-by: Simon Glass -
This driver supports GPIOs present on PM8916 PMIC.
There are 2 device drivers inside:
- GPIO driver (4 "generic" GPIOs)
- Keypad driver that presents itself as GPIO with 2 inputs (power and reset)Signed-off-by: Mateusz Kulikowski
Reviewed-by: Simon Glass
Tested-by: Simon Glass -
This PMIC is connected on SPMI bus so needs SPMI support enabled.
Signed-off-by: Mateusz Kulikowski
Reviewed-by: Simon Glass
Tested-by: Simon Glass -
Support SPMI arbiter on Qualcomm Snapdragon devices.
Signed-off-by: Mateusz Kulikowski
Reviewed-by: Simon Glass
Tested-by: Simon Glass -
This patch adds emulated spmi bus controller with part of
pm8916 pmic on it to sandbox and tests validating SPMI uclass.Signed-off-by: Mateusz Kulikowski
Reviewed-by: Simon Glass -
This driver is able to reconfigure OTG controller into HOST mode.
Board can add board-specific initialization as board_prepare_usb().
It requires USB_ULPI_VIEWPORT enabled in board configuration.Signed-off-by: Mateusz Kulikowski
Acked-by: Marek Vasut
Tested-by: Simon Glass -
Add support for SD/eMMC controller present on some Qualcomm Snapdragon
devices. This controller implements SDHCI 2.0 interface but requires
vendor-specific initialization.
Driver works in PIO mode as ADMA is not supported by U-Boot (yet).Signed-off-by: Mateusz Kulikowski
Reviewed-by: Simon Glass
Tested-by: Simon Glass -
Add support for gpio controllers on Qualcomm Snapdragon devices.
This devices are usually called Top Level Mode Multiplexing in
Qualcomm documentation.Signed-off-by: Mateusz Kulikowski
Reviewed-by: Simon Glass
Tested-by: Simon Glass -
This driver works in "new" Data Mover UART mode, so
will be compatible with modern Qualcomm chips only.Signed-off-by: Mateusz Kulikowski
Reviewed-by: Simon Glass
Tested-by: Simon Glass -
Add some basic clarification that the dev.key file generated by OpenSSL
contains both the public and private key, and further highlight that
the certificate generated here contains the public key only.Signed-off-by: Andreas Dannenberg
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Different sections in the document suggest flattened image tree blob
files have a file name extension of .itb. Fix the list of file extensions
to reflect that.Signed-off-by: Andreas Dannenberg
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- Move most of the flags required into LLVM_RELFLAGS to test at build
time instead of requiring them to be passed in.
- Update doc/README.clang to reflect this
- Switch to rpi_2 as the example as it's closer to working out of the
box than rpi is.Cc: Jeroen Hofstee
Signed-off-by: Tom Rini
27 Mar, 2016
1 commit
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It is possible to compile and run the sandbox target with clang
currently, so document that as well.Cc: Jeroen Hofstee
Signed-off-by: Tom Rini
24 Mar, 2016
2 commits
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Now everything is done to load a raw U-Boot proper image instead of
an mkimage-processed one (as far as I tested on NAND, eMMC, NOR).The SPL already knows the load address of the U-Boot proper without
parsing its uImage header because the load address is defined by
CONFIG_SYS_TEXT_BASE, assuming that the two images are generated from
the same build.My main motivation of this switch is to use u-boot-with-spl.bin, a
concatenation of u-boot-spl.bin and u-boot.bin. (I wish there were
a concatenation of u-boot-spl.bin and u-boot.img...) Anyway, this
commit would be useful for one-shot image burn.Signed-off-by: Masahiro Yamada
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Commit 3cb9abc9c512 ("ARM: uniphier: update U-Boot file names in
workflow") missed to update these two sentences. Fix them now.Replace u-boot-spl-dtb.bin and u-boot-dtb.img with u-boot-spl.bin
and u-boot.img, respectively.Signed-off-by: Masahiro Yamada
23 Mar, 2016
1 commit
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Signed-off-by: Vagrant Cascadian
Acked-by: Marek Vasut
Reviewed-by: Simon Glass
Reviewed-by: Tom Rini
22 Mar, 2016
1 commit
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Add support of address parity for DDR4 UDIMM or discrete memory.
It requires to configurate corresponding MR5[2:0] and
TIMING_CFG_7[PAR_LAT]. Parity can be turned on by hwconfig,
e.g. hwconfig=fsl_ddr:parity=on.Signed-off-by: Shengzhou Liu
Reviewed-by: York Sun
17 Mar, 2016
7 commits
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This adds basic support for chromebook_samus. This is the 2015 Pixel and
is based on an Intel broadwell platform.Supported so far are:
- Serial
- SPI flash
- SDRAM init (with MRC cache)
- SATA
- Video (on the internal LCD panel)
- KeyboardVarious less-visible drivers are provided to make the above work (e.g. PCH,
power control and LPC).The platform requires various binary blobs which are documented in the
README. The major missing feature is USB3 since the existing U-Boot support
does not work correctly with Intel XHCI controllers.Signed-off-by: Simon Glass
Reviewed-by: Bin Meng -
Update a few points which have become out-of-date.
Signed-off-by: Simon Glass
Reviewed-by: Bin Meng -
GPIO pins need to be set up on start-up. Add a driver to provide this,
configured from the device tree.The binding is slightly different from the existing ICH6 binding, since that
is quite verbose. The new binding should be just as extensible.Signed-off-by: Simon Glass
Acked-by: Bin Meng -
Make a few minor updates to make the meaning clearer.
Signed-off-by: Simon Glass
Reviewed-by: Bin Meng -
Add a driver which sets up the pin configuration on x86 devices with an ICH6
(or later) Platform Controller Hub.The driver is not in the pinctrl uclass due to some oddities of the way x86
devices work:- The GPIO controller is not present in I/O space until it is set up
- This is done by writing a register in the PCH
- The PCH has a driver which itself uses PCI, another driver
- The pinctrl uclass requires that a pinctrl device be available before any
other device can be probedIt would be possible to work around the limitations by:
- Hard-coding the GPIO address rather than reading it from the PCH
- Using special x86 PCI access to set the GPIO address in the PCHHowever it is not clear that this is better, since the pin configuration
driver does not actually provide normal pin configuration services - it
simply sets up all the pins statically when probed. While this remains the
case, it seems better to use a syscon uclass instead. This can be probed
whenever it is needed, without any limitations.Also add an 'invert' property to support inverting the input.
Signed-off-by: Simon Glass
Reviewed-by: Bin Meng -
It is useful to automate the process of converting code from coreboot a
little. Add a sed script which performs some common transformations.Signed-off-by: Simon Glass
Acked-by: Bin Meng -
Boting SeaBIOS is done via U-Boot's bootelf command. Document this.
Signed-off-by: Bin Meng
Reviewed-by: Simon Glass
16 Mar, 2016
2 commits
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To preserve all cover letter knowledge of the status on UEFI payload
support, let's add some sections to README.efi.Signed-off-by: Alexander Graf
v3 -> v4:
- Add section about config options
- s/10kb/10KB/ -
By now the code to only have a single page table level with 64k page
size and 42 bit address space is no longer used by any board in tree,
so we can safely remove it.To clean up code, move the layerscape mmu code to the new defines,
removing redundant field definitions.Signed-off-by: Alexander Graf
15 Mar, 2016
1 commit