11 Jan, 2018
1 commit
09 Aug, 2017
1 commit
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Fix the size calculation in the verify boot. The original
patch 266b5c0cdbd1150cf5e6bde0d473e5d2f0f60812 was merged
but this was not the correct version. The correct version
subtracted the header.Fixes: 266b5c0cdbd1 ("arm: am33xx: security: adds auth support for encrypted images")
Signed-off-by: Madan Srinivas
Signed-off-by: Dan Murphy
26 Jul, 2017
1 commit
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The image address passed to secure_boot_verify_image() may not be
cacheline aligned, round the address down to the nearest cacheline.Signed-off-by: Andrew F. Davis
25 Jul, 2017
1 commit
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This patch adds support for authentication of both plain
text and encrypted binaries. A new SECDEV package is needed
to enable encryption of binaries by default for AM3x.The ROM authentication API detects encrypted images at
runtime and automatically decrypts the image if the
signature verification passes.Addition of encryption on AM3x results in a change in the
image format. On AM4x, AM5x and, on AM3x devices signing
clear test images, the signature is appended to the end of the
binary.On AM3x, when the SECDEV package is used to create signed
and encrypted images, the signature is added as a header
to the start of the binary. So the binary size calculation
has been updated to reflect this change.The signing tools and encrypted image format for AM3x
cannot be changed to behave like AM4x and AM5x to
maintain backward compatibility with older Sitara
M-Shield releases.Adding encryption support also increases the size of
the PPA. As the SPL is loaded right after the PPA for
any peripheral boot, this increase in PPA size results
in the SPL load address moving by 0x200 bytes (for UART boot).
Memory boot modes like MMC are not affected, as the ROM
loads the PPA and SPL in two separate steps.Acked-by: Andrew F. Davis
Signed-off-by: Madan Srinivas
24 Jul, 2017
1 commit
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commit 6183b29559107650cb38f905e069a93ff9da1d7d upstream
Currently while setting the vsel value for dcdc1 and dcdc2
the driver is wrongly masking the entire 8 bits in the process
clearing PFM (bit7) field as well. Hence describe an appropriate
mask for vsel field and modify only those bits in the vsel
mask.Source: http://www.ti.com/lit/ds/symlink/tps65218.pdf
Signed-off-by: Keerthy
Fixes: 86db550b38 ("power: Add support for the TPS65218 PMIC")
Reviewed-by: Jaehoon Chung
20 Jul, 2017
1 commit
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The layout of the eMMC has been updated in commit 33348a383808
("ARM: ti: Update layout for MMC and eMMC (env and dfu)"). This patch
updates the GPT table for android to match this new layout for the
following items:
- xloader,
- u-boot
- the u-boot environment variables
- the DTB (aka os args, aka environment)Signed-off-by: Jean-Jacques Hiblot
17 Jul, 2017
1 commit
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Increase PHY autonegoiate time from current 8 seconds
to 16 seconds. On some Ethernet switches, 2 times out
of 100, the Micrel KSZ9031 PHY on AM572x IDK board seems
to take more than 8 seconds to establish link at gigabit
speeds.Since the timeout is only an upper bound on waiting time
it should not affect users who do not face the same
problem.Signed-off-by: Sekhar Nori
15 Jul, 2017
5 commits
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The PMMC firmware should be bundled with the FIT image for HS devices,
remove the steps that load and install this firmware outside of FIT.Signed-off-by: Andrew F. Davis
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The PMMC firmware should be bundled into a FIT image on HS
devices to allow authentication/decryption, add a handler to
process this PMMC firmware.Signed-off-by: Andrew F. Davis
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Add a new image type representing TI Power Management
Micro-Controller (PMMC) Firmware image type.Signed-off-by: Andrew F. Davis
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Supporting DDR52 and HS200 modes requires that the pinmux and iodelays are
properly programmed with platform specific values. This commit provides the
same information as the dts does but in a manner that's usable by the SPL.Signed-off-by: Jean-Jacques Hiblot
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AM571x supports DDR running at 666MHz. Right now it is
clocked at 532MHz which is lower than what is supported.
In order to have maximum performance on AM571-IDK,
switch DDR to 666MHz.Signed-off-by: Steve Kipisz
Signed-off-by: Lokesh Vutla
03 Jul, 2017
3 commits
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On AM43xx devices, QSPI boot is XIP and we use a single stage bootloader.
Add a defconfig for this.Signed-off-by: Andrew F. Davis
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Add ddr voltage rail (dcdc3) configuration. Set the dcdc3
DDR supply to 1.35V.Signed-off-by: Keerthy
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Some boards like am437x-gp-evm require dcdc3 also to be configured
as it feeds on to ddr. Hence add the capability as well.Signed-off-by: Keerthy
27 Jun, 2017
5 commits
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gpio2 is used to detect lcd based on which pin mux is done in SPL.
gpio7 is used to enable vtt regulator. Enable these teo gpio nodes
in SPL.Signed-off-by: Lokesh Vutla
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Enable spl_early_init() so that spl can use
DT very early during boot.Signed-off-by: Lokesh Vutla
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ROM stores the boot params information in a known location
and passes it to SPL. This information needs to be copied
very early during boot or else there is a chance of getting
corrupted by SPL. So move this boot device detection very early
during boot.Signed-off-by: Lokesh Vutla
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Calls to IS_ENABLED() on a non-y/n option will always be false, even
when set. We can correct this by adding a new bool value that is set
based on the conditions required for SPL_STACK_R_MALLOC_SIMPLE_LEN to be
set instead.Fixes: 340f418acd11 ("spl: Add spl_early_init()")
Reported-by: Lokesh Vutla
Signed-off-by: Tom Rini -
At present malloc_base/_limit/_ptr are not initialised in spl_init() when
we call spl_init() in board_init_f(). This is due to a recent change aimed
at avoiding overwriting the malloc area set up on some boards by
spl_relocate_stack_gd().However if CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN is not defined, we now
skip setting up the memory area in spl_init() which is obviously wrong.To fix this, add a new function spl_early_init() which can be called in
board_init_f().Fixes: b3d2861e (spl: Remove overwrite of relocated malloc limit)
Signed-off-by: Eddie Cai
Rewrote spl_{,early_}init() to avoid duplicate code:
Rewrite/expand commit message:
Signed-off-by: Simon Glass
Reviewed-by: Eddie Cai
17 Jun, 2017
1 commit
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The size of the secure image does not include the size of the
header, subtract this out before we move the image or we grab
extra data after the image.Signed-off-by: Andrew F. Davis
15 Jun, 2017
2 commits
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commit 7a53a1a8115b upstream
The problems with the current DFU layout are:
MMC: The space allocated for u-boot is too small for the latest u-boot
(>750KB). We need to increase it. eMMC uses a much bigger area (2MB).
eMMC: region "u-boot.img.raw" overlaps the environment area and the region
"spl-os-image.raw".
both: region "spl-os-image.raw" is quite small and can't handle android
kernelsFixing this requires growing some regions and moving others.
Care has been taken to leave some room for further growth of
"spl-os-args.raw".
Also the "env" now appears in the dfu so that it's apparent that the
region is not free space that can be used to grow "u-boot.img.raw".
The MLO region is 0x100 sectors wide but the 0x100 are unused in case the
MLO comes too overflow this areas.
The total space allocated for those raw binaries is 16MB, of which 13+MB
are reserved for the kernel image.Signed-off-by: Jean-Jacques Hiblot
Reviewed-by: Tom Rini
Reviewed-by: Sam Protsenko -
On secure devices the initial secure software may install a firewall at
the end of DRAM, define protected RAM to avoid space.Signed-off-by: Andrew F. Davis
10 Jun, 2017
1 commit
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commit 5cb52e573f ("board: am335x: Introduce scale_vcores")
updated voltages of each board based on efuse. It updated
beagle bone specific voltages under the condition board_is_bone().
But this is true only for BeagleBoneWhite. Due to which voltages
are not configured for BBB, BBW as wrong device is being probed.So create a common function board_is_beaglebonex() which includes
am335x based beagle family. Use this for updating voltages.Also remove extra if condition for selecting voltages which is
done later using a switch case and match usb current limit as
before the commit 5cb52e573f.Fixes: 5cb52e573f ("board: am335x: Introduce scale_vcores")
Reported-by: Emmanuel Vadot
Signed-off-by: Lokesh Vutla
07 Jun, 2017
2 commits
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When fat command is enabled, enable fatwrite too
so U-Boot can create new files too.Signed-off-by: Sekhar Nori
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As per the datasheet[1] available for DDR2 part on board
the OMAP-L138 LCDK, the tXSNR (exit self refresh to a
non-read command) is 137.5 ns. This corresponds to a
value of 20 to be written to T_XSNR register field of
OMAP-L138's DDR configuration. The DDR2 is at 150 MHz.Fix this. The correct value also appears on the initialization
scripts (called CCS GEL files) available on TI's wiki pages[2][1] http://www.samsung.com/global/business/semiconductor/file/product/ds_k4t1gxx4qf_rev12-0.pdf
[2] http://processors.wiki.ti.com/index.php/L138/C6748_Development_Kit_(LCDK)#CCS_XML_.26_GEL_FilesReviewed-by: Tom Rini
Signed-off-by: Sekhar Nori
24 May, 2017
6 commits
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Abort CPSW driver init when auto-negotiation of link
times out. Currently, the code ignores return status
of phy_startup(), and goes ahead with network operation
(like DHCP) even though the link may be down.Instead, abort init process if link is down or if there
is another error, so phy_startup() can easily be retried
again. This also helps quick fallback to next network interface
(like USB RNDIS) without inordinate delay.Tested on AM571x IDK and AM335x BeagleBone black.
Reviewed-by: Tom Rini
Signed-off-by: Sekhar Nori -
When the OP-TEE image is built for secure paging the load address may be
in SRAM, remove checks that prevent this.Signed-off-by: Harinarayan Bhatta
Signed-off-by: Andrew F. Davis -
Now that we can specify DT nodes that can be used in spl, mark
all necessary nodes as u-boot,dm-spl.Signed-off-by: Lokesh Vutla
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Now that we can specify DT nodes that can be used in spl, mark
all necessary nodes as u-boot,dm-spl.Signed-off-by: Lokesh Vutla
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Right now the u-boot,dm-pre-reloc flag will make each marked node
always appear in both spl and tpl. But systems needing an additional
tpl might have special constraints for each, like the spl needing to
be very tiny.So introduce two additional flags to mark nodes for only spl or tpl
environments and introduce a function dm_fdt_pre_reloc to automate
the necessary checks in code instances checking for pre-relocation
flags.The behaviour of the original flag stays untouched and still marks
a node for both spl and tpl.Signed-off-by: Heiko Stuebner
Reviewed-by: Simon Glass
Tested-by: Kever Yang -
Update vcores for am571-idk board.
Reported-by: Steve Kipisz
Signed-off-by: Keerthy
Signed-off-by: Lokesh Vutla
22 May, 2017
8 commits
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commit 8dc8d294b "drivers: mmc: downgrade the current mode if error rate
becomes too high" breaks the compilation of mmc core when CONFIG_BLK is
enabled.Signed-off-by: Jean-Jacques Hiblot
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commit 17c9a1c121e7d78d820fdb4f7ca070f53e23c29a upstream
Signed-off-by: Jean-Jacques Hiblot
Reviewed-by: Tom Rini -
commit 3d673ffce32cc65c7fe046c0c314566385a5d586 upstream
This is a preparation work for the support of CONFIG_BLK.
Signed-off-by: Jean-Jacques Hiblot
Reviewed-by: Tom Rini -
commit dc09127a26f67044c5c6b5062163f95e35d06a3b upstream
Signed-off-by: Jean-Jacques Hiblot
Reviewed-by: Tom Rini -
commit ae000e231e35ef6e1ec4f7a3e477cf4bef2cf189 upstream
For consistency, use an accessor to access the private data. Also for the
same reason, rename all priv_data to priv.Signed-off-by: Jean-Jacques Hiblot
Reviewed-by: Tom Rini -
One some keystone2 platforms like K2G ICE, there is an option
to switch between 24MHz or 25MHz as sysclk. But the existing
driver assumes it is always 24MHz. Add support for getting
all reference clocks dynamically by reading boot pins.Signed-off-by: Lokesh Vutla
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K2G supports various sysclk frequencies which can be
determined using sysboot pins. PLLs should be configured
based on this sysclock frequency. Add PLL configurations
for all supported sysclk frequencies.Signed-off-by: Lokesh Vutla
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am335x supports various sysclk frequencies which can be determined
using sysboot pins. PLLs should be configures based on this
sysclk frequency. Add PLL configurations for all supported
frequencies.Signed-off-by: Lokesh Vutla