17 Dec, 2014
5 commits
-
Defer probe till remowkup_m3_pm_ops are populated. This is to ensure
that wkup_m3 is probed after the wkup_m3_pm_ops are populated by the
mach-omap2 init call. This ensures clean initialization of m3.Signed-off-by: Keerthy
Acked-by: Dave Gerlach -
The offsets for i2c voltage scaling sequence were being set directly
into IPC register 5 and being passed for all PM operations. This is
incorrect as only DeepSleep0 should scale voltage, not standby or
cpuidle. Instead we should store the value when it is calculated
and only pass for DeepSleep operation, not cpuidle operation.Signed-off-by: Dave Gerlach
-
Add ti,mbox-send-noirq to wkup_m3 mailbox so that messages using
wkup_m3 mailbox are sent without triggering any further interrupts.
This is required to be able to send multiple messages to the WkupM3
after the mailbox usage logic adjustment in the wkup_m3_ipc driver.Signed-off-by: Keerthy
Acked-by: Dave Gerlach
[s-anna@ti.com: revise commit description]
Signed-off-by: Suman Anna -
Add ti,mbox-send-noirq to wkup_m3 mailbox so that messages using
wkup_m3 mailbox are sent without triggering any further interrupts.
This is needed to achieve lower power numbers during CPU idle on
AM33xx.Tested-by: Keerthy
Signed-off-by: Dave Gerlach
[s-anna@ti.com: revise commit description]
Signed-off-by: Suman Anna -
The mailbox framework controls the transmission queue and requires
either its controller implementations or clients to run the state
machine for the Tx queue. The OMAP mailbox controller uses a Tx-ready
interrupt as the equivalent of a Tx-done interrupt to run this Tx
queue state-machine.The WkupM3 processor on AM33xx and AM43xx SoCs is used to offload
certain PM tasks, like doing the necessary operations for Device
PM suspend/resume or for entering lower c-states during cpuidle.The CPUIdle on AM33xx requires the messages to be sent without
having to trigger the Tx-ready interrupts, as the interrupt
would immediately terminate the CPUIdle operation. Support for
this has been added by introducing a DT quirk, "ti,mbox-send-noirq"
and using it to modify the normal OMAP mailbox controller behavior
on the sub-mailboxes used to communicate with the WkupM3 remote
processor. This also requires the wkup_m3_ipc driver to adjust
its mailbox usage logic to run the Tx state machine.NOTE:
- AM43xx does not communicate with WkupM3 for CPU Idle, so is
not affected by this behavior. But, it uses the same IPC driver
for PM suspend/resume functionality, so requires the quirk as
well, because of changes to the common wkup_m3_ipc driver.Signed-off-by: Dave Gerlach
[s-anna@ti.com: revise logic and update comments/patch description]
Signed-off-by: Suman Anna
07 Nov, 2014
2 commits
-
Correct returning IRQ_HANDLED unconditionally in the irq handler.
Return IRQ_NONE for some interrupt which we do not expect to be
handled in this handler. This prevents kernel stalling with back
to back spurious interrupts.Signed-off-by: Keerthy
Acked-by: Nishanth Menon -
On certain SoCs such as AM437x SoC, L3_noc error registers are
maintained in power domain such as per domain which looses context as part
of low power state such as RTC+DDR mode. On these platforms when we
mask interrupts which we cannot handle, the source of these interrupts
still remain on resume, however, the flag mux registers now contain
thier reset value (unmasked) - this breaks the system with infinite
interrupts since we do not these interrupts to take place ever again.To handle this: restore the masking of interrupts which we have
already recorded in the system as ones we cannot handle.Fixes: 654fa7979b5db9a44b8 ("bus: omap_l3_noc: ignore masked out unclearable targets")
Signed-off-by: Keerthy
Acked-by: Nishanth Menon
06 Nov, 2014
1 commit
-
Value 23 indicates all OPPs. Add that to the configuration.
Based on Vayu Speed grade document revision 0.2 (May 30, 2014).
Signed-off-by: Nishanth Menon
Acked-by: Dave Gerlach
31 Oct, 2014
2 commits
-
Systems that do not support poweroff (for instance, DRA7), cannot
recover from a software triggered thermal shutdown. In such cases
fall back to restarting the system, and leave it to the bootloader
to handle the scenario.[j-keerthy@ti.com] ported to 3.14 and tested
Signed-off-by: Keerthy
Signed-off-by: Subramaniam Chanderashekarapuram -
These functions are indended for use by drivers and should be available
also when the driver is built as a module.Cc: MyungJoo Ham
Cc: Kyungmin Park
Signed-off-by: Ørjan Eide
[nm@ti.com: just a simple backport]
Signed-off-by: Nishanth Menon
10 Oct, 2014
3 commits
-
On older PMICs the reset value of the DCDC3 voltage was different.
Fix DCDC3 volatge to 1.5V which is the right value to be supplied by
DCDC3 for all the production boards(Version 1.4+).Signed-off-by: Keerthy
-
On older PMICs the reset value of the DCDC3 voltage was different.
Fix DCDC3 volatge to 1.5V which is the right value to be supplied by
DCDC3 for all the production boards(Version 1.4+).This fixes the boot hang issue during the regulator initialization stage.
Tested-by: Aparna Balasubramanian
Signed-off-by: Keerthy -
On older PMICs the reset value of the DCDC3 voltage was different.
Fix DCDC3 volatge to 1.5V which is the right value to be supplied by
DCDC3 for all the production boards(Version 1.4+).Tested-by: George Cherian
Signed-off-by: Keerthy
09 Oct, 2014
2 commits
-
Access the three registers that we need to access after EMIF is placed
in DDR to make sure they are present in TLB to avoid a miss and walk of
page table in DDR, which is not possible once DDR is shut off and will
lead to a hang in suspend path if attempted.Signed-off-by: Dave Gerlach
-
According to AM437x Silicon Errata document (SPRZ408, June 2014)
Advisory 11, the SoC also suffers from the potential Asynchronous Bridge
Corruption issues seen on OMAP4, which were corrected by 137d105d5. Add
omap_bus_sync style accesses to DRAM and SRAM to avoid hangs during
suspend/resume by perfoming one strongly ordered write to DRAM and one
to SRAM before calling WFI in the suspend path assembly code.Signed-off-by: Dave Gerlach
18 Sep, 2014
13 commits
-
Save/restore of these registers is needed so that certain features
like PRCM io-chain will still function properly after rtc-only mode.Signed-off-by: Tero Kristo
-
NOTE: We will not support CPUIDLE for DRA7 for the current release.
It does seem that allowing MPU to hit CSWR in the middle of active
usecase causes DSS to generate underflows, Audio to generate glitches.Initially, it was suspected to be 'CDDS: OMAP5430-2.0BUG00954'
(OMAPS00292300)
Description:
(note: this is regularization of a problem open since 29-Jun-12)
We are observing that when we enabled cpuidle (where MPU can hit
CSWR state), we are observing DSS FIFO underflow error. After some
debugging we found that if we enable DSS->EMIF static dependency
(OR disable emif HW_AUTO), we no longer see this issue. This is a
temporary hack to work around the problem and definitely cannot be a
solution.WA:
At OPP_NOM use fast_lock=0 and keep MDLL clock always on (clock gating
disabled)But, it was quickly determined that even after deny_idle of EMIF or
applying DSS to EMIF static dependency, this issue is not resolved.Further, on J6eco: Why does hitting the 0x4d000000 address range on
j6eco appears to clean the underflows up? We dont have clear answers or
a root cause yet.So, disabling CPU_IDLE for now. revert this hack after rootcause. Also
note a related side effect of not having CPUIDLE is marked here:
http://marc.info/?l=linux-omap&m=141046424815199&w=2
Which is also valid for DRA7 and OMAP5 and is under investigation.See bugs: D-01233, D-01739 s/w discussions.
Signed-off-by: Nishanth Menon
-
Bump pm firmware minimum version requirement to 0x189 to include support
for wkup_m3_rproc auxdata and IO daisy chain wake.Signed-off-by: Dave Gerlach
-
CPUIdle does not get disabled until noirq suspend, but am33xx_pm_enter
is called early in the suspend sequence, which configures the wkup_m3
for deep sleep before waiting for the m3_irq2 interrupt. On AM43xx, this
interrupt is triggerred by a WFI instruction with MPU clockdomain set to
HW_AUTO and SCU set to low power state, which is the same condition present
in cpuidle state.If system attempts to enter cpuidle c-state during
suspend path (happens very rarely) the system will hang because it will
gate the MPU clock and pass control to wkup_m3 which attempts to put
system in DeepSleep when it is not actually prepared.By using cpu_idle_poll_ctrl we can prevent cpuidle from entering
c-states during the suspend path and prevent this hang. Also useful on
AM33xx to prevent suspend from failing without a hang due to cpuidle
reconfiguring the wkup_m3 during suspend for mpu pll bypass only rather
than deep sleep.Signed-off-by: Dave Gerlach
-
Use suspend support present in cpufreq core to set suspend frequency
and configure suspend frequency to first defined OPP.Signed-off-by: Dave Gerlach
-
Move auxdata region in wkup_m3 dmem to take over first 0x100 bytes of
logbuf region. Otherwise i2c sequences get overwritten occasionally.Signed-off-by: Dave Gerlach
-
Patch 95306a5: ARM: OMAP2: sleep43xx: Set MPU Clockdomain to HW_AUTO
after suspend attempted to set MPU clockdomain to HW_AUTO but was
writing to the virtual address rather than physical address after
resume. Correct code to use physical address as the MMU has not yet been
turned on.Signed-off-by: Dave Gerlach
-
Add IO wake up support. The patch reuses the omap4 based
IO wake up support and enables the same on AM43XX.Signed-off-by: Keerthy
-
PRM_IO_PMCTRL_OFFSET need not be same for all SOCs hence
remove hardcoding and use the value provided by the omap_prcm_irq_setup
structure.Signed-off-by: Keerthy
-
Add nr_irqs check to extend support to single core SOCs.
Signed-off-by: Keerthy
-
This was incorrectly saving the irq status registers, instead of the
irq enable.Signed-off-by: Tero Kristo
-
Add PRCM int16 as the wake up source.
Signed-off-by: Keerthy
-
Conflicts:
arch/arm/boot/dts/dra72x.dtsi
arch/arm/boot/dts/dra74x.dtsiSigned-off-by: Tero Kristo
12 Sep, 2014
3 commits
-
AM43XX and DRA7XX has RTC. Enabling the same in Kconfig.
Signed-off-by: Tero Kristo
Signed-off-by: Lokesh Vutla -
of_clk_add_provider makes an internal copy of the parent_names property
while its called, thus it is no longer needed after this call and can
be freed.Signed-off-by: Tero Kristo
-
These are incorrectly using OMAP3 variant, which causes build errors with
AMx3xx only builds.Signed-off-by: Tero Kristo
11 Sep, 2014
2 commits
-
OMAP4 has a finer counter granularity, which allows for a delay of 1000ms
in the thermal zone polling intervals. OMAP5/DRA7 have different counter
mechanism, which allows at maximum a 500ms timer. Adjust the cpu thermal
zone accordingly for OMAP5/DRA7.Signed-off-by: Tero Kristo
-
Use ti,am3352-rtc for rtc node on am335x so that the driver knows to
enable am3352 specific features, including those needed for wakeup
from deep sleep mode.Signed-off-by: Dave Gerlach
04 Sep, 2014
1 commit
-
Boot time access to the RTC will cause a hang on boards that don't have
RTC module. Fixed by checking the DTS status of RTC device in the PM
code before attempting to access the RTC.Signed-off-by: Tero Kristo
Cc: Felipe Balbi
Cc: Dave Gerlach
Cc: Keerthy
03 Sep, 2014
1 commit
-
The added ti,gpio-gate-clock is a basic clock that can be enabled and
disabled trough a gpio output. The DT binding document for the clock
is also added. For EPROBE_DEFER handling the registering of the clock
has to be delayed until of_clk_get() call time.Acked-by: Tero Kristo
Signed-off-by: Jyri Sarha
02 Sep, 2014
2 commits
-
The power line feeding the SD card is also used by other devices on the EVM.
Use generic name instead of mmc2_3v3 so when other devices want to use the
same regulator it will look a bit better.Signed-off-by: Peter Ujfalusi
-
mmc2_3v3 is derived from the board level evm_3v3_sw power line and other
components are using the same line for their power needs.Signed-off-by: Peter Ujfalusi
01 Sep, 2014
3 commits
-
[ Upstream commit 7d5fc85d961b807c799786afd175f5d964a2109f ]
When setting the rate of a clock, by default the clock framework will
change the parent of the clock to the most suitable one in
__clk_mux_determine_rate() (most suitable by looking at the clock rate).This is a rather dangerous default, and causes problems on AM43x when
using display and ethernet. There are multiple ways to select the clock
muxes on AM43x, and some of those clock paths have the same source
clocks for display and ethernet. When changing the clock rate for the
display subsystem, the clock framework decides to change the display mux
from the dedicated display PLL to a shared PLL which is used by the
ethernet, and then changes the rate of the shared PLL, breaking the
ethernet.As I don't think there ever is a case where we want the clock framework
to automatically change the parent clock of a clock mux, this patch sets
the CLK_SET_RATE_NO_REPARENT for all ti,mux-clocks.Signed-off-by: Tomi Valkeinen
Signed-off-by: Jyri Sarha -
Adding support for using generic of_clk_init caused an issue with retrying
clock init, in such way that retry init was never attempted for failed
clocks. Fixed by exporting the retry init call into its own driver API,
and calling this after of_clk_init from low level IO init.Fixes: e80e55ebbf2856614 ("clk: ti: change clock init to use generic of_clk_init")
Reported-by: Carlos Hernandez
Signed-off-by: Tero Kristo
Tested-by: Sekhar Nori -
Add appropriate scale-data-fw names for all am43xx platforms.
Signed-off-by: Dave Gerlach
