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arch/arm/cpu/armv7/socfpga/clock_manager.c
15.8 KB
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/* * Copyright (C) 2013 Altera Corporation <www.altera.com> * * SPDX-License-Identifier: GPL-2.0+ */ #include <common.h> #include <asm/io.h> #include <asm/arch/clock_manager.h> |
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DECLARE_GLOBAL_DATA_PTR; |
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static const struct socfpga_clock_manager *clock_manager_base = |
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(struct socfpga_clock_manager *)SOCFPGA_CLKMGR_ADDRESS; |
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|
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static void cm_wait_for_lock(uint32_t mask) |
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{ register uint32_t inter_val; |
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uint32_t retry = 0; |
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do { inter_val = readl(&clock_manager_base->inter) & mask; |
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if (inter_val == mask) retry++; else retry = 0; if (retry >= 10) break; } while (1); |
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} /* function to poll in the fsm busy bit */ |
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static void cm_wait_for_fsm(void) |
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{ while (readl(&clock_manager_base->stat) & CLKMGR_STAT_BUSY) ; } /* * function to write the bypass register which requires a poll of the * busy bit */ |
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static void cm_write_bypass(uint32_t val) |
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{ writel(val, &clock_manager_base->bypass); cm_wait_for_fsm(); } /* function to write the ctrl register which requires a poll of the busy bit */ |
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static void cm_write_ctrl(uint32_t val) |
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{ writel(val, &clock_manager_base->ctrl); cm_wait_for_fsm(); } /* function to write a clock register that has phase information */ |
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static void cm_write_with_phase(uint32_t value, uint32_t reg_address, uint32_t mask) |
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{ /* poll until phase is zero */ while (readl(reg_address) & mask) ; writel(value, reg_address); while (readl(reg_address) & mask) ; } /* * Setup clocks while making no assumptions about previous state of the clocks. * * Start by being paranoid and gate all sw managed clocks * Put all plls in bypass * Put all plls VCO registers back to reset value (bandgap power down). * Put peripheral and main pll src to reset value to avoid glitch. * Delay 5 us. * Deassert bandgap power down and set numerator and denominator * Start 7 us timer. * set internal dividers * Wait for 7 us timer. * Enable plls * Set external dividers while plls are locking * Wait for pll lock * Assert/deassert outreset all. * Take all pll's out of bypass * Clear safe mode * set source main and peripheral clocks * Ungate clocks */ void cm_basic_init(const cm_config_t *cfg) { uint32_t start, timeout; /* Start by being paranoid and gate all sw managed clocks */ /* * We need to disable nandclk * and then do another apb access before disabling * gatting off the rest of the periperal clocks. */ writel(~CLKMGR_PERPLLGRP_EN_NANDCLK_MASK & |
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readl(&clock_manager_base->per_pll.en), &clock_manager_base->per_pll.en); |
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/* DO NOT GATE OFF DEBUG CLOCKS & BRIDGE CLOCKS */ writel(CLKMGR_MAINPLLGRP_EN_DBGTIMERCLK_MASK | CLKMGR_MAINPLLGRP_EN_DBGTRACECLK_MASK | CLKMGR_MAINPLLGRP_EN_DBGCLK_MASK | CLKMGR_MAINPLLGRP_EN_DBGATCLK_MASK | CLKMGR_MAINPLLGRP_EN_S2FUSER0CLK_MASK | CLKMGR_MAINPLLGRP_EN_L4MPCLK_MASK, |
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&clock_manager_base->main_pll.en); |
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|
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writel(0, &clock_manager_base->sdr_pll.en); |
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/* now we can gate off the rest of the peripheral clocks */ |
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writel(0, &clock_manager_base->per_pll.en); |
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/* Put all plls in bypass */ |
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cm_write_bypass(CLKMGR_BYPASS_PERPLL | CLKMGR_BYPASS_SDRPLL | CLKMGR_BYPASS_MAINPLL); |
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|
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/* Put all plls VCO registers back to reset value. */ writel(CLKMGR_MAINPLLGRP_VCO_RESET_VALUE & ~CLKMGR_MAINPLLGRP_VCO_REGEXTSEL_MASK, |
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&clock_manager_base->main_pll.vco); |
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writel(CLKMGR_PERPLLGRP_VCO_RESET_VALUE & ~CLKMGR_PERPLLGRP_VCO_REGEXTSEL_MASK, |
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&clock_manager_base->per_pll.vco); |
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writel(CLKMGR_SDRPLLGRP_VCO_RESET_VALUE & ~CLKMGR_SDRPLLGRP_VCO_REGEXTSEL_MASK, |
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&clock_manager_base->sdr_pll.vco); |
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/* * The clocks to the flash devices and the L4_MAIN clocks can * glitch when coming out of safe mode if their source values * are different from their reset value. So the trick it to * put them back to their reset state, and change input * after exiting safe mode but before ungating the clocks. */ writel(CLKMGR_PERPLLGRP_SRC_RESET_VALUE, |
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&clock_manager_base->per_pll.src); |
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writel(CLKMGR_MAINPLLGRP_L4SRC_RESET_VALUE, |
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&clock_manager_base->main_pll.l4src); |
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/* read back for the required 5 us delay. */ |
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readl(&clock_manager_base->main_pll.vco); readl(&clock_manager_base->per_pll.vco); readl(&clock_manager_base->sdr_pll.vco); |
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/* * We made sure bgpwr down was assert for 5 us. Now deassert BG PWR DN * with numerator and denominator. */ |
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writel(cfg->main_vco_base, &clock_manager_base->main_pll.vco); writel(cfg->peri_vco_base, &clock_manager_base->per_pll.vco); writel(cfg->sdram_vco_base, &clock_manager_base->sdr_pll.vco); |
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/* * Time starts here * must wait 7 us from BGPWRDN_SET(0) to VCO_ENABLE_SET(1) */ |
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start = get_timer(0); /* timeout in unit of us as CONFIG_SYS_HZ = 1000*1000 */ timeout = 7; /* main mpu */ |
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writel(cfg->mpuclk, &clock_manager_base->main_pll.mpuclk); |
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/* main main clock */ |
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writel(cfg->mainclk, &clock_manager_base->main_pll.mainclk); |
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/* main for dbg */ |
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writel(cfg->dbgatclk, &clock_manager_base->main_pll.dbgatclk); |
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/* main for cfgs2fuser0clk */ writel(cfg->cfg2fuser0clk, |
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&clock_manager_base->main_pll.cfgs2fuser0clk); |
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/* Peri emac0 50 MHz default to RMII */ |
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writel(cfg->emac0clk, &clock_manager_base->per_pll.emac0clk); |
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/* Peri emac1 50 MHz default to RMII */ |
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writel(cfg->emac1clk, &clock_manager_base->per_pll.emac1clk); |
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/* Peri QSPI */ |
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writel(cfg->mainqspiclk, &clock_manager_base->main_pll.mainqspiclk); |
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writel(cfg->perqspiclk, &clock_manager_base->per_pll.perqspiclk); |
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/* Peri pernandsdmmcclk */ |
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writel(cfg->mainnandsdmmcclk, &clock_manager_base->main_pll.mainnandsdmmcclk); |
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writel(cfg->pernandsdmmcclk, |
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&clock_manager_base->per_pll.pernandsdmmcclk); |
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/* Peri perbaseclk */ |
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writel(cfg->perbaseclk, &clock_manager_base->per_pll.perbaseclk); |
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/* Peri s2fuser1clk */ |
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writel(cfg->s2fuser1clk, &clock_manager_base->per_pll.s2fuser1clk); |
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/* 7 us must have elapsed before we can enable the VCO */ while (get_timer(start) < timeout) ; /* Enable vco */ /* main pll vco */ |
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writel(cfg->main_vco_base | CLKMGR_MAINPLLGRP_VCO_EN, |
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&clock_manager_base->main_pll.vco); |
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/* periferal pll */ |
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writel(cfg->peri_vco_base | CLKMGR_MAINPLLGRP_VCO_EN, |
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&clock_manager_base->per_pll.vco); |
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/* sdram pll vco */ |
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writel(cfg->sdram_vco_base | CLKMGR_MAINPLLGRP_VCO_EN, &clock_manager_base->sdr_pll.vco); |
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/* L3 MP and L3 SP */ |
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writel(cfg->maindiv, &clock_manager_base->main_pll.maindiv); |
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writel(cfg->dbgdiv, &clock_manager_base->main_pll.dbgdiv); |
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writel(cfg->tracediv, &clock_manager_base->main_pll.tracediv); |
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/* L4 MP, L4 SP, can0, and can1 */ |
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writel(cfg->perdiv, &clock_manager_base->per_pll.div); |
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writel(cfg->gpiodiv, &clock_manager_base->per_pll.gpiodiv); |
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#define LOCKED_MASK \ (CLKMGR_INTER_SDRPLLLOCKED_MASK | \ CLKMGR_INTER_PERPLLLOCKED_MASK | \ CLKMGR_INTER_MAINPLLLOCKED_MASK) cm_wait_for_lock(LOCKED_MASK); /* write the sdram clock counters before toggling outreset all */ writel(cfg->ddrdqsclk & CLKMGR_SDRPLLGRP_DDRDQSCLK_CNT_MASK, |
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&clock_manager_base->sdr_pll.ddrdqsclk); |
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writel(cfg->ddr2xdqsclk & CLKMGR_SDRPLLGRP_DDR2XDQSCLK_CNT_MASK, |
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&clock_manager_base->sdr_pll.ddr2xdqsclk); |
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writel(cfg->ddrdqclk & CLKMGR_SDRPLLGRP_DDRDQCLK_CNT_MASK, |
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&clock_manager_base->sdr_pll.ddrdqclk); |
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writel(cfg->s2fuser2clk & CLKMGR_SDRPLLGRP_S2FUSER2CLK_CNT_MASK, |
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&clock_manager_base->sdr_pll.s2fuser2clk); |
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/* * after locking, but before taking out of bypass * assert/deassert outresetall */ |
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uint32_t mainvco = readl(&clock_manager_base->main_pll.vco); |
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/* assert main outresetall */ writel(mainvco | CLKMGR_MAINPLLGRP_VCO_OUTRESETALL_MASK, |
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&clock_manager_base->main_pll.vco); |
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|
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uint32_t periphvco = readl(&clock_manager_base->per_pll.vco); |
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/* assert pheriph outresetall */ writel(periphvco | CLKMGR_PERPLLGRP_VCO_OUTRESETALL_MASK, |
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&clock_manager_base->per_pll.vco); |
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/* assert sdram outresetall */ |
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writel(cfg->sdram_vco_base | CLKMGR_MAINPLLGRP_VCO_EN| CLKMGR_SDRPLLGRP_VCO_OUTRESETALL, |
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&clock_manager_base->sdr_pll.vco); |
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/* deassert main outresetall */ writel(mainvco & ~CLKMGR_MAINPLLGRP_VCO_OUTRESETALL_MASK, |
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&clock_manager_base->main_pll.vco); |
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/* deassert pheriph outresetall */ writel(periphvco & ~CLKMGR_PERPLLGRP_VCO_OUTRESETALL_MASK, |
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&clock_manager_base->per_pll.vco); |
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/* deassert sdram outresetall */ |
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writel(cfg->sdram_vco_base | CLKMGR_MAINPLLGRP_VCO_EN, &clock_manager_base->sdr_pll.vco); |
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/* * now that we've toggled outreset all, all the clocks * are aligned nicely; so we can change any phase. */ cm_write_with_phase(cfg->ddrdqsclk, |
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(uint32_t)&clock_manager_base->sdr_pll.ddrdqsclk, |
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CLKMGR_SDRPLLGRP_DDRDQSCLK_PHASE_MASK); /* SDRAM DDR2XDQSCLK */ cm_write_with_phase(cfg->ddr2xdqsclk, |
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(uint32_t)&clock_manager_base->sdr_pll.ddr2xdqsclk, |
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CLKMGR_SDRPLLGRP_DDR2XDQSCLK_PHASE_MASK); cm_write_with_phase(cfg->ddrdqclk, |
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(uint32_t)&clock_manager_base->sdr_pll.ddrdqclk, |
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CLKMGR_SDRPLLGRP_DDRDQCLK_PHASE_MASK); cm_write_with_phase(cfg->s2fuser2clk, |
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(uint32_t)&clock_manager_base->sdr_pll.s2fuser2clk, |
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CLKMGR_SDRPLLGRP_S2FUSER2CLK_PHASE_MASK); /* Take all three PLLs out of bypass when safe mode is cleared. */ |
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cm_write_bypass(0); |
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/* clear safe mode */ |
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cm_write_ctrl(readl(&clock_manager_base->ctrl) | CLKMGR_CTRL_SAFEMODE); |
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/* * now that safe mode is clear with clocks gated * it safe to change the source mux for the flashes the the L4_MAIN */ |
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writel(cfg->persrc, &clock_manager_base->per_pll.src); writel(cfg->l4src, &clock_manager_base->main_pll.l4src); |
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/* Now ungate non-hw-managed clocks */ |
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writel(~0, &clock_manager_base->main_pll.en); writel(~0, &clock_manager_base->per_pll.en); writel(~0, &clock_manager_base->sdr_pll.en); |
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/* Clear the loss of lock bits (write 1 to clear) */ writel(CLKMGR_INTER_SDRPLLLOST_MASK | CLKMGR_INTER_PERPLLLOST_MASK | CLKMGR_INTER_MAINPLLLOST_MASK, &clock_manager_base->inter); |
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} |
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static unsigned int cm_get_main_vco_clk_hz(void) |
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{ uint32_t reg, clock; /* get the main VCO clock */ reg = readl(&clock_manager_base->main_pll.vco); |
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clock = CONFIG_HPS_CLK_OSC1_HZ; clock /= ((reg & CLKMGR_MAINPLLGRP_VCO_DENOM_MASK) >> CLKMGR_MAINPLLGRP_VCO_DENOM_OFFSET) + 1; clock *= ((reg & CLKMGR_MAINPLLGRP_VCO_NUMER_MASK) >> CLKMGR_MAINPLLGRP_VCO_NUMER_OFFSET) + 1; |
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|
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return clock; } static unsigned int cm_get_per_vco_clk_hz(void) { uint32_t reg, clock = 0; /* identify PER PLL clock source */ reg = readl(&clock_manager_base->per_pll.vco); |
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reg = (reg & CLKMGR_PERPLLGRP_VCO_SSRC_MASK) >> CLKMGR_PERPLLGRP_VCO_SSRC_OFFSET; |
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if (reg == CLKMGR_VCO_SSRC_EOSC1) clock = CONFIG_HPS_CLK_OSC1_HZ; else if (reg == CLKMGR_VCO_SSRC_EOSC2) clock = CONFIG_HPS_CLK_OSC2_HZ; else if (reg == CLKMGR_VCO_SSRC_F2S) clock = CONFIG_HPS_CLK_F2S_PER_REF_HZ; /* get the PER VCO clock */ reg = readl(&clock_manager_base->per_pll.vco); |
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clock /= ((reg & CLKMGR_PERPLLGRP_VCO_DENOM_MASK) >> CLKMGR_PERPLLGRP_VCO_DENOM_OFFSET) + 1; clock *= ((reg & CLKMGR_PERPLLGRP_VCO_NUMER_MASK) >> CLKMGR_PERPLLGRP_VCO_NUMER_OFFSET) + 1; |
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return clock; } unsigned long cm_get_mpu_clk_hz(void) { uint32_t reg, clock; clock = cm_get_main_vco_clk_hz(); |
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/* get the MPU clock */ reg = readl(&clock_manager_base->altera.mpuclk); clock /= (reg + 1); reg = readl(&clock_manager_base->main_pll.mpuclk); clock /= (reg + 1); return clock; } unsigned long cm_get_sdram_clk_hz(void) { uint32_t reg, clock = 0; /* identify SDRAM PLL clock source */ reg = readl(&clock_manager_base->sdr_pll.vco); |
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reg = (reg & CLKMGR_SDRPLLGRP_VCO_SSRC_MASK) >> CLKMGR_SDRPLLGRP_VCO_SSRC_OFFSET; |
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if (reg == CLKMGR_VCO_SSRC_EOSC1) clock = CONFIG_HPS_CLK_OSC1_HZ; else if (reg == CLKMGR_VCO_SSRC_EOSC2) clock = CONFIG_HPS_CLK_OSC2_HZ; else if (reg == CLKMGR_VCO_SSRC_F2S) clock = CONFIG_HPS_CLK_F2S_SDR_REF_HZ; /* get the SDRAM VCO clock */ reg = readl(&clock_manager_base->sdr_pll.vco); |
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clock /= ((reg & CLKMGR_SDRPLLGRP_VCO_DENOM_MASK) >> CLKMGR_SDRPLLGRP_VCO_DENOM_OFFSET) + 1; clock *= ((reg & CLKMGR_SDRPLLGRP_VCO_NUMER_MASK) >> CLKMGR_SDRPLLGRP_VCO_NUMER_OFFSET) + 1; |
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/* get the SDRAM (DDR_DQS) clock */ reg = readl(&clock_manager_base->sdr_pll.ddrdqsclk); |
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reg = (reg & CLKMGR_SDRPLLGRP_DDRDQSCLK_CNT_MASK) >> CLKMGR_SDRPLLGRP_DDRDQSCLK_CNT_OFFSET; |
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clock /= (reg + 1); return clock; } unsigned int cm_get_l4_sp_clk_hz(void) { uint32_t reg, clock = 0; /* identify the source of L4 SP clock */ reg = readl(&clock_manager_base->main_pll.l4src); |
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reg = (reg & CLKMGR_MAINPLLGRP_L4SRC_L4SP) >> CLKMGR_MAINPLLGRP_L4SRC_L4SP_OFFSET; |
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if (reg == CLKMGR_L4_SP_CLK_SRC_MAINPLL) { |
5d8ad0cd3 arm: socfpga: clo... |
424 |
clock = cm_get_main_vco_clk_hz(); |
a832ddba5 arm: socfpga: clo... |
425 426 427 428 429 430 431 |
/* get the clock prior L4 SP divider (main clk) */ reg = readl(&clock_manager_base->altera.mainclk); clock /= (reg + 1); reg = readl(&clock_manager_base->main_pll.mainclk); clock /= (reg + 1); } else if (reg == CLKMGR_L4_SP_CLK_SRC_PERPLL) { |
5d8ad0cd3 arm: socfpga: clo... |
432 |
clock = cm_get_per_vco_clk_hz(); |
a832ddba5 arm: socfpga: clo... |
433 434 435 436 437 438 439 440 |
/* get the clock prior L4 SP divider (periph_base_clk) */ reg = readl(&clock_manager_base->per_pll.perbaseclk); clock /= (reg + 1); } /* get the L4 SP clock which supplied to UART */ reg = readl(&clock_manager_base->main_pll.maindiv); |
44428ab6a arm: socfpga: clo... |
441 442 |
reg = (reg & CLKMGR_MAINPLLGRP_MAINDIV_L4SPCLK_MASK) >> CLKMGR_MAINPLLGRP_MAINDIV_L4SPCLK_OFFSET; |
a832ddba5 arm: socfpga: clo... |
443 444 445 446 447 448 449 450 451 452 453 |
clock = clock / (1 << reg); return clock; } unsigned int cm_get_mmc_controller_clk_hz(void) { uint32_t reg, clock = 0; /* identify the source of MMC clock */ reg = readl(&clock_manager_base->per_pll.src); |
44428ab6a arm: socfpga: clo... |
454 455 |
reg = (reg & CLKMGR_PERPLLGRP_SRC_SDMMC_MASK) >> CLKMGR_PERPLLGRP_SRC_SDMMC_OFFSET; |
a832ddba5 arm: socfpga: clo... |
456 457 458 459 |
if (reg == CLKMGR_SDMMC_CLK_SRC_F2S) { clock = CONFIG_HPS_CLK_F2S_PER_REF_HZ; } else if (reg == CLKMGR_SDMMC_CLK_SRC_MAIN) { |
5d8ad0cd3 arm: socfpga: clo... |
460 |
clock = cm_get_main_vco_clk_hz(); |
a832ddba5 arm: socfpga: clo... |
461 462 463 464 465 |
/* get the SDMMC clock */ reg = readl(&clock_manager_base->main_pll.mainnandsdmmcclk); clock /= (reg + 1); } else if (reg == CLKMGR_SDMMC_CLK_SRC_PER) { |
5d8ad0cd3 arm: socfpga: clo... |
466 |
clock = cm_get_per_vco_clk_hz(); |
a832ddba5 arm: socfpga: clo... |
467 468 469 470 471 472 473 474 475 476 477 478 479 480 481 482 483 |
/* get the SDMMC clock */ reg = readl(&clock_manager_base->per_pll.pernandsdmmcclk); clock /= (reg + 1); } /* further divide by 4 as we have fixed divider at wrapper */ clock /= 4; return clock; } unsigned int cm_get_qspi_controller_clk_hz(void) { uint32_t reg, clock = 0; /* identify the source of QSPI clock */ reg = readl(&clock_manager_base->per_pll.src); |
44428ab6a arm: socfpga: clo... |
484 485 |
reg = (reg & CLKMGR_PERPLLGRP_SRC_QSPI_MASK) >> CLKMGR_PERPLLGRP_SRC_QSPI_OFFSET; |
a832ddba5 arm: socfpga: clo... |
486 487 488 489 |
if (reg == CLKMGR_QSPI_CLK_SRC_F2S) { clock = CONFIG_HPS_CLK_F2S_PER_REF_HZ; } else if (reg == CLKMGR_QSPI_CLK_SRC_MAIN) { |
5d8ad0cd3 arm: socfpga: clo... |
490 |
clock = cm_get_main_vco_clk_hz(); |
a832ddba5 arm: socfpga: clo... |
491 492 493 494 495 |
/* get the qspi clock */ reg = readl(&clock_manager_base->main_pll.mainqspiclk); clock /= (reg + 1); } else if (reg == CLKMGR_QSPI_CLK_SRC_PER) { |
5d8ad0cd3 arm: socfpga: clo... |
496 |
clock = cm_get_per_vco_clk_hz(); |
a832ddba5 arm: socfpga: clo... |
497 498 499 500 501 502 503 504 505 506 507 508 509 510 511 512 513 514 515 516 517 518 519 520 521 522 523 524 525 526 527 528 529 530 531 532 533 534 535 536 537 538 539 540 541 542 543 544 545 546 547 548 549 550 551 |
/* get the qspi clock */ reg = readl(&clock_manager_base->per_pll.perqspiclk); clock /= (reg + 1); } return clock; } static void cm_print_clock_quick_summary(void) { printf("MPU %10ld kHz ", cm_get_mpu_clk_hz() / 1000); printf("DDR %10ld kHz ", cm_get_sdram_clk_hz() / 1000); printf("EOSC1 %8d kHz ", CONFIG_HPS_CLK_OSC1_HZ / 1000); printf("EOSC2 %8d kHz ", CONFIG_HPS_CLK_OSC2_HZ / 1000); printf("F2S_SDR_REF %8d kHz ", CONFIG_HPS_CLK_F2S_SDR_REF_HZ / 1000); printf("F2S_PER_REF %8d kHz ", CONFIG_HPS_CLK_F2S_PER_REF_HZ / 1000); printf("MMC %8d kHz ", cm_get_mmc_controller_clk_hz() / 1000); printf("QSPI %8d kHz ", cm_get_qspi_controller_clk_hz() / 1000); printf("UART %8d kHz ", cm_get_l4_sp_clk_hz() / 1000); } int set_cpu_clk_info(void) { /* Calculate the clock frequencies required for drivers */ cm_get_l4_sp_clk_hz(); cm_get_mmc_controller_clk_hz(); gd->bd->bi_arm_freq = cm_get_mpu_clk_hz() / 1000000; gd->bd->bi_dsp_freq = 0; gd->bd->bi_ddr_freq = cm_get_sdram_clk_hz() / 1000000; return 0; } int do_showclocks(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) { cm_print_clock_quick_summary(); return 0; } U_BOOT_CMD( clocks, CONFIG_SYS_MAXARGS, 1, do_showclocks, "display clocks", "" ); |