29 Jul, 2011
1 commit
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Recieve/Receive
recieve/receive
Interupt/Interrupt
interupt/interrupt
Addres/Address
addres/addressSigned-off-by: Mike Williams
04 Apr, 2011
1 commit
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FSL PCIe controller v2.1:
- New MSI inbound window
- Same Inbound windows address as PCIe controller v1.xAdded new pit_t member(pmit) to struct ccsr_pci for MSI inbound window
FSL PCIe controller v2.2 and v2.3:
- Different addresses for PCIe inbound window 3,2,1
- Exposed PCIe inbound window 0
- New PCIe interrupt status registerAdded new Interrupt Status register to struct ccsr_pci & updated pit_t array
size to reflect the 4 inbound windows.To maintain backward compatiblilty, on V2.2 or greater controllers we
start with inbound window 1 and leave inbound 0 with its default value
(which maps to CCSRBAR).Signed-off-by: Prabhakar Kushwaha
Signed-off-by: Kumar Gala
29 Mar, 2011
1 commit
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The P1011, P1012, P1015, P1016, P1020, P1021, P1024, & P1025 SoCs require
that we initialize the SERDES registers if the lanes are configured for
PCIe. Additionally these devices PCIe controller do not support ASPM
and we have to explicitly disable it.Signed-off-by: Prabhakar Kushwaha
Signed-off-by: Kumar Gala
03 Feb, 2011
1 commit
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Signed-off-by: Wolfgang Denk
14 Jan, 2011
3 commits
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This change does the following:
- Adds printing of negotiated link width. This information can be
useful when debugging PCIe issues.
- Makes it optional for boards to implement board_serdes_name().
Previously boards that did not implement it would print unsightly
output such as "PCIE1: Connected to ..."
- Rewords the PCIe boot output to reduce line length and to make it
clear that the "base address XYZ" value refers to the base address of
the internal processor PCIe registers and not a standard PCI BAR
value.
- Changes "PCIE" output to the standard "PCIe"Before change:
PCIE1: connected to as Root Complex (base addr ef008000)
01:00.0 - 10b5:8518 - Bridge device
02:01.0 - 10b5:8518 - Bridge device
02:02.0 - 10b5:8518 - Bridge device
02:03.0 - 10b5:8518 - Bridge device
PCIE1: Bus 00 - 05
PCIE2: connected to as Endpoint (base addr ef009000)
PCIE2: Bus 06 - 06After change:
PCIe1: Root Complex of PEX8518 Switch, x4, regs @ 0xef008000
01:00.0 - 10b5:8518 - Bridge device
02:01.0 - 10b5:8518 - Bridge device
02:02.0 - 10b5:8518 - Bridge device
02:03.0 - 10b5:8518 - Bridge device
PCIe1: Bus 00 - 05
PCIe2: Endpoint of VPX Fabric A, x2, regs @ 0xef009000
PCIe2: Bus 06 - 06Signed-off-by: Peter Tyser
Signed-off-by: Kumar Gala -
Since all the PCIe controllers are connected over SERDES on the SoCs we
can utilize is_serdes_configured() to determine if a controller is
enabled. After which we can setup the ATMUs and LAWs for the controller
in a common fashion and allow board code to specify what the controller
is connected to for reporting reasons.We also provide a per controller (rather than all) for some systems that
may have special requirements.Finally, we refactor the code used by the P1022DS to utilize the new
generic code.Based on patch by: Li Yang
Signed-off-by: Kumar Gala
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Previously we passed in a specifically named struct pci_controller to
determine if we had setup the particular PCI bus. Now we can search for
the struct so we dont have to depend on the name or the struct being
statically allocated.Introduced new find_hose_by_cfg_addr() to get back a pci_controller struct
back by searching for it means we can do things like dynamically allocate
them or not have to expose the static structures to all users.Signed-off-by: Kumar Gala
Acked-by: Wolfgang Denk
15 Nov, 2010
3 commits
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The "Scanning PCI bus X" message doesn't provide any real useful
information, so remove it.Original output:
PCIE1: connected as Root Complex
Scanning PCI bus 01
04 01 8086 1010 0200 00
04 01 8086 1010 0200 00
03 00 10b5 8112 0604 00
02 01 10b5 8518 0604 00
02 02 10b5 8518 0604 00
08 00 1957 0040 0b20 00
07 00 10b5 8518 0604 00
09 00 10b5 8112 0604 00
07 01 10b5 8518 0604 00
07 02 10b5 8518 0604 00
06 00 10b5 8518 0604 00
02 03 10b5 8518 0604 00
01 00 10b5 8518 0604 00
PCIE1: Bus 00 - 0b
PCIE2: connected as Root Complex
Scanning PCI bus 0d
0d 00 1957 0040 0b20 00
PCIE2: Bus 0c - 0dUpdated output:
PCIE1: connected as Root Complex
04 01 8086 1010 0200 00
04 01 8086 1010 0200 00
03 00 10b5 8112 0604 00
02 01 10b5 8518 0604 00
02 02 10b5 8518 0604 00
08 00 1957 0040 0b20 00
07 00 10b5 8518 0604 00
09 00 10b5 8112 0604 00
07 01 10b5 8518 0604 00
07 02 10b5 8518 0604 00
06 00 10b5 8518 0604 00
02 03 10b5 8518 0604 00
01 00 10b5 8518 0604 00
PCIE1: Bus 00 - 0b
PCIE2: connected as Root Complex
0d 00 1957 0040 0b20 00
PCIE2: Bus 0c - 0dSigned-off-by: Peter Tyser
CC: galak@kernel.crashing.org -
Previously boards used a variety of indentations, newline styles, and
colon styles for the PCI information that is printed on bootup. This
patch unifies the style to look like:...
NAND: 1024 MiB
PCIE1: connected as Root Complex
Scanning PCI bus 01
04 01 8086 1010 0200 00
04 01 8086 1010 0200 00
03 00 10b5 8112 0604 00
02 01 10b5 8518 0604 00
02 02 10b5 8518 0604 00
08 00 1957 0040 0b20 00
07 00 10b5 8518 0604 00
09 00 10b5 8112 0604 00
07 01 10b5 8518 0604 00
07 02 10b5 8518 0604 00
06 00 10b5 8518 0604 00
02 03 10b5 8518 0604 00
01 00 10b5 8518 0604 00
PCIE1: Bus 00 - 0b
PCIE2: connected as Root Complex
Scanning PCI bus 0d
0d 00 1957 0040 0b20 00
PCIE2: Bus 0c - 0d
In: serial
...Signed-off-by: Peter Tyser
CC: wd@denx.de
CC: sr@denx.de
CC: galak@kernel.crashing.org -
Previously fsl_pci_init_port() always assumed that a port was a PCIe
port and would incorrectly print messages for a PCI port such as the
following on bootup:
PCI1: 32 bit, 33 MHz, sync, host, arbiter
Scanning PCI bus 00
PCIE1 on bus 00 - 00This change corrects the output of fsl_pci_init_port():
PCI1: 32 bit, 33 MHz, sync, host, arbiter
Scanning PCI bus 00
PCI1 on bus 00 - 00Signed-off-by: Peter Tyser
22 Oct, 2010
1 commit
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Add a new 'pci enum' command which re-enumerates the PCI buses. This
command is enabled via the CONFIG_CMD_PCI_ENUM define and can be useful
in boards with FPGAs connected via PCI/PCIe, boards that support PCI
hot-plugging, or during PCI debug.Also enable the 'pci enum' command for X-ES's Freescale-based boards.
Signed-off-by: John Schmoller
Signed-off-by: Peter Tyser
Acked-by: Kumar Gala
Acked-by: Wolfgang Denk
20 Jul, 2010
1 commit
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Previously we used an alias the pci node to determine which node to
fixup or delete. Now we use the new fdt_node_offset_by_compat_reg to
find the node to update.Additionally, we replace the code in each board with a single macro call
that makes assumes uniform naming and reduces duplication in this area.Signed-off-by: Kumar Gala
07 Apr, 2010
1 commit
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If the PCI controller wasn't configured or enabled delete from the
device tree (include its alias).For the case that we didn't even configure u-boot with knowledge of
the controller we can use the fact that the pci_controller pointer
is NULL to delete the node in the device tree. We determine that
a controller was not setup (because of HW config) based on the fact
that cfg_addr wasn't setup.Signed-off-by: Kumar Gala
06 Jan, 2010
1 commit
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All users of is_fsl_pci_agent have been converted to fsl_is_pci_agent
that uses the standard PCI programming model to determine host vs
agent/end-point.Signed-off-by: Kumar Gala
04 Nov, 2009
2 commits
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commit 70ed869e broke fsl pcie end-point initialization.
Returning 0 is not correct. The function must return the first free
bus number for the next controller.fsl_pci_init() must still be called and a bus allocated even if the
controller is an end-point.Signed-off-by: Ed Swarthout
Acked-by: Vivek Mahajan
Signed-off-by: Kumar Gala -
This reverts commit 70ed869ea5f6b1d13d7b140c83ec0dcd8a127ddc.
There isn't any need to modify the API for fsl_pci_init_port to pass the
status of host/agent(end-point) status. We can determine that
internally to fsl_pci_init_port. Revert the patch that makes the API
change.Signed-off-by: Kumar Gala
27 Oct, 2009
1 commit
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Originally written by Jason Jin and Mingkai Hu for mpc8536.
When QorIQ based board is configured as a PCIe agent, then unlock/enable
inbound PCI configuration cycles and init a 4K inbound memory window;
so that a PCIe host can access the PCIe agents SDRAM at address 0x0* Supported in fsl_pci_init_port() after adding pcie_ep as a param
* Revamped copyright in drivers/pci/fsl_pci_init.c
* Mods in 85xx based board specific pci init after this changeSigned-off-by: Vivek Mahajan
Signed-off-by: Kumar Gala
25 Sep, 2009
1 commit
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General code cleanup to use in/out IO accessors as well as making
the code that prints out info sane between board and generic fsl pci
code.Signed-off-by: Kumar Gala
29 Aug, 2009
5 commits
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fsl_pci_init_port can be called from board specific PCI initialization
routines to setup the PCI (or PCIe) controller. This will reduce code
redundancy in most of the 85xx/86xx FSL board ports that setup PCI.Signed-off-by: Poonam Aggrwal
Signed-off-by: Kumar Gala -
The old PCI ATMU setup code would just mimic the PCI regions into the
ATMU registers. For simple memory maps in which all memory, MMIO, etc
space fit into 4G this works ok. However there are issues with we have
>4G of memory as we know can't access all of memory and we need to
ensure that PCICSRBAR (PEXCSRBAR on PCIe) isn't overlapping with
anything since we can't turn it off.We first setup outbound windows based on what the board code setup
in the pci regions for MMIO and IO access. Next we place PCICSRBAR
below the MMIO window. After which we try to setup the inbound windows
to map as much of memory as possible.On PCIe based controllers we are able to overmap the ATMU setup since
RX & TX links are separate but report the proper amount of inbound
address space to the region tracking to ensure there is no overlap.On PCI based controllers we use as many inbound windows as available to
map as much of the memory as possible.Additionally we changed all the CCSR register access to use proper IO
accessor functions. Also had to add CONFIG_SYS_CCSRBAR_PHYS to some
86xx platforms that didn't have it defined.Signed-off-by: Kumar Gala
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Change the code to use the PCIe capabilities register to determine if we
are a PCIe controller or not. Additionally cleaned up some white space
and formatting in the file.Signed-off-by: Kumar Gala
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Every platform that calls fsl_pci_init calls fsl_pci_setup_inbound_windows
before it calls fsl_pci_init. There isn't any reason to just call it
from fsl_pci_init and simplify things a bit.Signed-off-by: Kumar Gala
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Every platform that calls fsl_pci_init calls pci_setup_indirect before
it calls fsl_pci_init. There isn't any reason to just call it from
fsl_pci_init and simplify things a bit.Signed-off-by: Kumar Gala
04 Apr, 2009
1 commit
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Rename the pci header for FSL HW so we can move some prototypes
in there and stop doing explicit externsSigned-off-by: Kumar Gala
08 Feb, 2009
1 commit
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The PCI_REGION_MEMORY and PCI_REGION_MEM are a bit to similar and
can be confusing when reading the code.Rename PCI_REGION_MEMORY to PCI_REGION_SYS_MEMORY to clarify its used
for system memory mapping purposes.Signed-off-by: Kumar Gala
20 Dec, 2008
1 commit
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Add fsl_pci_config_unlock() function to enable a
PCI/PCIe interface configured in agent/endpoint mode to
respond to inbound PCI configuration cycles.Signed-off-by: Peter Tyser
10 Dec, 2008
1 commit
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fsl_pci_init.c: In function 'fsl_pci_setup_inbound_windows':
fsl_pci_init.c:122: warning: comparison is always true due to limited range of data typeThe check only makes sense if we are CONFIG_PHYS_64BIT
Signed-off-by: Kumar Gala
04 Dec, 2008
1 commit
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The current code will cause the creation of a 4GB window
starting at 0 if we have more than 4GB of RAM installed,
which overlaps with PCI_MEM space and causes pci_bus_to_phys()
to return erroneous information. Limit the size to 4GB - 1;
which causes the code to create one 2GB and one 1GB window
instead.Signed-off-by: Becky Bruce
Signed-off-by: Kumar Gala
Acked-by: Andy Fleming
28 Oct, 2008
2 commits
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The existing code has a few errors that need to be fixed in
order to support large RAM sizes. Fix those, and add a
comment to make it clearer.Signed-off-by: Becky Bruce
Acked-by: Kumar Gala -
Signed-off-by: Kumar Gala
25 Oct, 2008
3 commits
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Signed-off-by: Kumar Gala
Signed-off-by: Andrew Fleming-AFLEMING -
Add a common setup function that determines the pci_region(s) based
on how much memory we have in the system.Signed-off-by: Kumar Gala
Signed-off-by: Andrew Fleming-AFLEMING -
* PCI Inbound window was setup incorrectly. The PCI address and system
address were swapped. The PCI address should be setting piwar/piwbear
and the system address should be setting pitar.* Removed masking of addresses to allow for system address to support
system address & PCI address >32-bits* Set PIWBEAR & POTEAR to allow for full 64-bit PCI addresses
* Respect the PCI_REGION_PREFETCH for inbound windows
Signed-off-by: Kumar Gala
Signed-off-by: Andrew Fleming-AFLEMING
14 Oct, 2008
1 commit
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Signed-off-by: Ed Swarthout
Acked-by: Andy Fleming
13 Aug, 2008
1 commit
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Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD
14 Jul, 2008
1 commit
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Signed-off-by: Wolfgang Denk
24 Apr, 2008
1 commit
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pme_msg_det exists only on PCIe controllers only set it if we are a "bridge".
Signed-off-by: Kumar Gala
12 Dec, 2007
1 commit
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On the MPC85xx boards that have PCIe enable the PCIe errata fix.
(MPC8544DS, MPC8548CDS, MPC8568MDS).Signed-off-by: Kumar Gala
25 Nov, 2007
1 commit
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Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD