07 Jun, 2014

2 commits

  • updates documentation with explanation on how to select ECC schemes.

    Signed-off-by: Pekon Gupta

    pekon gupta
     
  • GPMC controller needs to be configured based on bus-width of the NAND device
    connected to it. Also, dynamic detection of NAND bus-width from on-chip ONFI
    parameters is not possible in following situations:
    SPL: SPL NAND drivers does not support ONFI parameter reading.
    U-boot: GPMC controller iniitalization is done in omap_gpmc.c:board_nand_init()
    which is called before probing for devices, hence any ONFI parameter
    information is not available during GPMC initialization.

    Thus, OMAP NAND driver expected board developers to explicitely write GPMC
    configurations specific to NAND device attached on board in board files itself.
    But this was troublesome for board manufacturers as they need to dive into
    lengthy platform & SoC documents to find details of GPMC registers and
    appropriate configurations to get NAND device working.

    This patch instead adds existing CONFIG_SYS_NAND_BUSWIDTH_16BIT to board config
    hich indicates that connected NAND device has x16 bus-width. And then based on
    this config GPMC driver itself initializes itself based on NAND bus-width. This
    keeps board developers free from knowing GPMC controller specific internals.

    Signed-off-by: Pekon Gupta

    pekon gupta
     

02 Jun, 2014

1 commit


28 May, 2014

1 commit

  • This adds driver support for the TPS65090 PMU. Support includes
    hooking into the pmic infrastructure so that the pmic commands
    can be used on the console. The TPS65090 supports the following
    functionality:

    - fet enable/disable/querying
    - getting and setting of charge state

    Even though it is connected to the pmic infrastructure it does
    not hook into the pmic charging charging infrastructure.

    The device tree binding is from Linux, but only a small subset of
    functionality is supported.

    Signed-off-by: Tom Wai-Hong Tam
    Signed-off-by: Hatim Ali
    Signed-off-by: Katie Roberts-Hoffman
    Signed-off-by: Rong Chang
    Signed-off-by: Sean Paul
    Signed-off-by: Vincent Palatin
    Signed-off-by: Aaron Durbin
    Signed-off-by: Simon Glass
    Signed-off-by: Minkyu Kang

    Tom Wai-Hong Tam
     

27 May, 2014

1 commit


24 May, 2014

1 commit


23 May, 2014

1 commit


17 May, 2014

1 commit


16 May, 2014

1 commit


13 May, 2014

2 commits


10 May, 2014

2 commits


09 May, 2014

1 commit


08 May, 2014

1 commit

  • This patch contains an implementation of the fastboot protocol on the
    device side and documentation. This is based on USB download gadget
    infrastructure. The fastboot function implements the getvar, reboot,
    download and reboot commands. What is missing is the flash handling i.e.
    writting the image to media.

    v3 (Rob Herring):
    This is based on http://patchwork.ozlabs.org/patch/126798/ with the
    following changes:
    - Rebase to current mainline and updates for current gadget API
    - Use SPDX identifiers for licenses
    - Traced the history and added missing copyright to cmd_fastboot.c
    - Use load_addr/load_size for transfer buffer
    - Allow vendor strings to be optional
    - Set vendor/product ID from config defines
    - Allow Ctrl-C to exit fastboot mode
    v4:
    - Major re-write to use the USB download gadget. Consolidated function
    code to a single file.
    - Moved globals into single struct.
    - Use puts and putc as appropriate.
    - Added CONFIG_USB_FASTBOOT_BUF_ADDR and CONFIG_USB_FASTBOOT_BUF_SIZE to
    set the fastboot transfer buffer.
    v5:
    - Add CONFIG option documentation to README
    - Rebase using new downloader registration

    Signed-off-by: Sebastian Andrzej Siewior
    Signed-off-by: Rob Herring

    Sebastian Siewior
     

26 Apr, 2014

1 commit


23 Apr, 2014

2 commits

  • Add support of 2 stage NAND/SD boot loader using SPL framework.
    PBL initialise the internal SRAM and copy SPL, this further
    initialise DDR using SPD and environment and copy u-boot from
    NAND/SD to DDR, finally SPL transfer control to u-boot.
    NOR uses CS1 instead of CS2 when NAND boot, fix it.

    Signed-off-by: Shaohui Xie
    Reviewed-by: York Sun

    Shaohui Xie
     
  • Add support of 2 stage NAND boot loader using SPL framework.
    here, PBL initialise the internal SRAM and copy SPL(160KB). This further
    initialise DDR using SPD and environment and copy u-boot(768 KB) from NAND to DDR.
    Finally SPL transer control to u-boot.

    Initialise/create followings required for SPL framework
    - Add spl.c which defines board_init_f, board_init_r
    - update tlb and ddr accordingly

    Signed-off-by: Prabhakar Kushwaha
    Reviewed-by: York Sun

    Prabhakar Kushwaha
     

20 Apr, 2014

1 commit


18 Apr, 2014

18 commits


08 Apr, 2014

1 commit


04 Apr, 2014

1 commit


03 Apr, 2014

1 commit