13 Aug, 2015
40 commits
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This adds a simple pmic driver for the hi6553 pmic which is used in
conjunction with the hi6220 SoC on the hikey board. Eventually this
driver will be updated to be a proper UCLASS PMIC driver which
can parse the voltages direct from device tree.Signed-off-by: Peter Griffin
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This patch adds basic pinmux support for the hi6220 SoC,
which is found on the hikey board.Signed-off-by: Peter Griffin
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This patch adds the header files which will be used in the subsquent
board / drivers to enable support for hi6220 hikey board.Signed-off-by: Peter Griffin
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This patch adds support for the GPIO perif found on hi6220
SoC.Signed-off-by: Peter Griffin
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Modify the data pointer type from ulong* to u32*.
For arm64 type "ulong" could be 64-bit. Then in line 89 of common/cmd_source.c:
"while (*data++);" data will point to the next 64 bits each time. As the uImage
file generated by mkimage tool keeps the same data format in either 32-bit or 64-bit
platform, the difference would cause failure in 64-bit platform.Signed-off-by: Gong Qianyu
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Make the cast explicit for "warning: cast to pointer from integer of different size".
Signed-off-by: Gong Qianyu
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The semantics for non-static functions declared inline have changed in
gcc5, causing the empty functions not to be emitted as an external
symbol.Since lowlevel_init() is only referenced from start.S, it should not be
declared inline at all.Reported-by: Otavio Salvador
Tested-by: Otavio Salvador
[trini: Reword commit message]
Signed-off-by: Tom Rini -
Since all the clocks are defined common, and has the same logic to get
the frequencies, use a common definition for for clk_get_rate().Reviewed-by: Tom Rini
Signed-off-by: Lokesh Vutla -
Remove unused external clocks and make a common definition
for all keystone platforms.Reviewed-by: Tom Rini
Signed-off-by: Lokesh Vutla -
This is just a cosmetic change that makes
the calling of pll init code looks much cleaner.Reviewed-by: Tom Rini
Reviewed-by: Vitaly Andrianov
Signed-off-by: Lokesh Vutla -
Register Base addresses are same for PLLs in all
keystone platforms. If a PLL is not available, the corresponding
register addresses are marked as reserved.
Hence use a common definition.Reviewed-by: Tom Rini
Signed-off-by: Lokesh Vutla -
Use common devspeed and armspeed definitions.
Also fix reading efuse bootrom register.Reviewed-by: Tom Rini
Reviewed-by: Vitaly Andrianov
Signed-off-by: Lokesh Vutla -
There are two types of PLL for all keystone platforms:
Main PLL, Secondary PLL. Instead of duplicating the same definition
for each secondary PLL, have a common function which does
initialization for both PLLs. And also add proper register
definitions.Reviewed-by: Tom Rini
Signed-off-by: Lokesh Vutla -
Add print_cpuinfo() function and enable
CONFIG_DISPLAY_CPUINFO for keystone platforms,
so that cpu info can be displayed during boot.Reviewed-by: Tom Rini
Reviewed-by: Vitaly Andrianov
Signed-off-by: Lokesh Vutla -
Add proper register definition for JTAG ID and
cleanup cpu_is_* functions.Reviewed-by: Tom Rini
Reviewed-by: Vitaly Andrianov
Signed-off-by: Lokesh Vutla -
DRA72x processor variants are single core and it does not export ACP[1].
Hence, we have no source for generating an external snoop requests which
appear to be key to the deadlock in DRA72x design.Since we build the same image for DRA74x and DRA72x platforms, lets
runtime detect and disable the workaround (in favor of performance) on
DRA72x platforms.[1] http://infocenter.arm.com/help/topic/com.arm.doc.ddi0438i/BABIAJAG.html
Suggested-by: Richard Woodruff
Suggested-by: Brad Griffis
Reviewed-by: Brad Griffis
Signed-off-by: Nishanth Menon -
Implement logic for ACR(Auxiliary Control Register) configuration using
ROM Code smc service.Suggested-by: Richard Woodruff
Suggested-by: Brad Griffis
Reviewed-by: Brad Griffis
Signed-off-by: Nishanth Menon -
Add workaround for Cortex-A15 ARM erratum 801819 which says in summary
that "A livelock can occur in the L2 cache arbitration that might
prevent a snoop from completing. Under certain conditions this can
cause the system to deadlock. "Recommended workaround is as follows:
Do both of the following:1) Do not use the write-back no-allocate memory type.
2) Do not issue write-back cacheable stores at any time when the cache
is disabled (SCTLR.C=0) and the MMU is enabled (SCTLR.M=1). Because it
is implementation defined whether cacheable stores update the cache when
the cache is disabled it is not expected that any portable code will
execute cacheable stores when the cache is disabled.For implementations of Cortex-A15 configured without the “L2 arbitration
register slice” option (typically one or two core systems), you must
also do the following:3) Disable write-streaming in each CPU by setting ACTLR[28:25] = 0b1111
So, we provide an option to disable write streaming on OMAP5 and DRA7.
It is a rare condition to occur and may be enabled selectively based
on platform acceptance of risk.Applies to: A15 revisions r2p0, r2p1, r2p2, r2p3 or r2p4 and REVIDR[3]
is set to 0.Note: certain unicore SoCs *might* not have REVIDR[3] not set, but
might not meet the condition for the erratum to occur when they donot
have ACP (Accelerator Coherency Port) hooked to ACE (AXI Coherency
Extensions). Such SoCs will need the work around handled in the SoC
specific manner, since there is no ARM generic manner to detect such
configurations.Based on ARM errata Document revision 18.0 (22 Nov 2013)
Suggested-by: Richard Woodruff
Suggested-by: Brad Griffis
Reviewed-by: Brad Griffis
Signed-off-by: Nishanth Menon -
This switches the Integrator boards over to using the device model
for its serial ports.Cc: Masahiro Yamada
Signed-off-by: Linus Walleij -
Remove the CONFIG_DM_USB limitation to enable cache support functions.
Tested on SAMA5D3x-EK board.Signed-off-by: Josh Wu
Acked-by: Hans de Goede -
Current many cpu use the same flush_cache() function, which just call
the flush_dcache_range().
So implement a weak flush_cache() for all the cpus to use.In original weak flush_cache() in arch/arm/lib/cache.c, there has some
code for ARM1136 & ARM926ejs. But in the arch/arm/cpu/arm1136/cpu.c and
arch/arm/cpu/arm926ejs/cache.c, there implements a real flush_cache()
function as well. That means the original code for ARM1136 & ARM926ejs
in weak flush_cache() of arch/arm/lib/cache.c is totally useless.So in this patch remove such code in flush_cache() and only call
flush_dcache_range().Signed-off-by: Josh Wu
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Since some driver like ohci, lcd used dcache functions. But some ARM
cpu don't implement the invalidate_dcache_range()/flush_dcache_range()
functions.To avoid compiling errors this patch adds an weak empty stub function
for all ARM cpu in arch/arm/lib/cache.c.
And ARM cpu still can implemnt its own cache functions on the cpu folder.Signed-off-by: Josh Wu
Reviewed-by: York Sun -
Since some driver like ohci, lcd used dcache functions. But m68k don't
implement the invalidate_dcache_range()/flush_dcache_range() functions.To avoid compiling errors this patch adds an weak empty stub function
for all m68k cpu.Also each cpu can implement its own implementation. If not implemented
then by default is using an empty function.Signed-off-by: Josh Wu
Acked-by: Angelo Dureghello -
gpio.h - Added missing copyright in few files.
rsa-mod-exp.h - Corrected copyright in the file.
fsl_sec.h - Added missing license in files
drivers/crypto/fsl/Makefile - Removed the incomplete GPLv2 license and replaced it with GPLv2+ licenseSigned-off-by: Ruchika Gupta
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Signed-off-by: Stefano Babic
Reviewed-by: Tom Rini -
Signed-off-by: Stefano Babic
Reviewed-by: Tom Rini -
mcx was not updated according to changes in
NAND driver.Signed-off-by: Stefano Babic
Reviewed-by: Tom Rini -
The menuconfig for drivers are getting more and more cluttered
and unreadable because too many entries are displayed in a single
flat menu. Use hierarchic menu for each category.Signed-off-by: Masahiro Yamada
Reviewed-by: Simon Glass
[trini: Update to apply again in a few places, drop USB hunk]
Signed-off-by: Tom Rini -
The new bitfield value must not be higher than its mask.
Signed-off-by: Codrin Ciubotariu
Reviewed-by: Joe Hershberger -
Now that mailbox driver supports cache flush and invalidation, we can
enable dcache.Signed-off-by: Alexander Stein
Acked-by: Stephen Warren
Tested-by: Stephen Warren -
This adds dcache support for dwc2. The DMA buffers must be DMA aligned and
is flushed for outgoing transactions before starting transfer. For
ingoing transactions it is invalidated after the transfer has finished.Signed-off-by: Alexander Stein
Acked-by: Stephen Warren
[trini: Update to apply again on top of DM patches]
Signed-off-by: Tom Rini -
When using dcache the setup data for the mailbox must be actually written
into memory before calling into firmware. Thus flush and invalidate the
memory.Signed-off-by: Alexander Stein
Acked-by: Stephen Warren
Tested-by: Stephen Warren -
The mailbox buffer is required to be at least 16 bytes aligned, but for
cache invalidation and/or flush it needs to be cacheline aligned.
Use ALLOC_CACHE_ALIGN_BUFFER for all mailbox buffer allocations.Signed-off-by: Alexander Stein
Acked-by: Stephen Warren
Tested-by: Stephen Warren -
The cacheline is always 32 bytes for arm1176 CPUs, so define it at board
config level for cache handling code.
The ARM Cortex-A7 has a dcache line size of 64 bytes.Signed-off-by: Alexander Stein
Acked-by: Stephen Warren
Tested-by: Stephen Warren -
As both cores are similar merge the cache handling code for both CPUs
to arm11 directory.Signed-off-by: Alexander Stein
Acked-by: Stephen Warren
Tested-by: Stephen Warren
[trini: Add hunk to arch/arm/cpu/arm1136/Makefile]
Signed-off-by: Tom Rini -
Apparently lcd_panel_disable is not defined anywhere, so no config for
an arm1136 board would have set CONFIG_LCD. Remove the unused code.Signed-off-by: Alexander Stein
Acked-by: Stephen Warren
Tested-by: Stephen Warren -
Using the twl4030 keypad allows booting directly into some special boot modes,
such as recovery or fastboot. the VOL+ key will trigger a boot to recovery while
the VOL- key will trigger a boot to fastboot.The G (gesture) key remains unused at this point.
Signed-off-by: Paul Kocialkowski
Reviewed-by: Tom Rini -
In most cases, userspace will attempt to power off the device with HALT instead
of POWER_OFF, which triggers a reset instead of a proper power off from the
TWL4030. Hence, it is up to the bootloader to actually turn the device off when
there is no reason to turn it on.A reboot identified with the OMAP reboot mode bits set is acceptable, as well as
a power on reason from either the power button, USB or charger plug.Other cases should trigger a power off. Note that for the U-Boot reset command
to take effect, we have to fill-in the OMAP reboot bits.Signed-off-by: Paul Kocialkowski
Reviewed-by: Tom Rini -
This adds support for resetting the device on a long press on the power button.
Signed-off-by: Paul Kocialkowski
Reviewed-by: Tom Rini -
This adds support for the fastboot USB gadget, including flashing to the
internal MMC and reboot to bootloader or not.Signed-off-by: Paul Kocialkowski
Reviewed-by: Tom Rini
[trini: Update to use Kconfig for MUSB]
Signed-off-by: Tom Rini
