20 Jan, 2016
1 commit
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Remove duplicated SDRAM_INTERVAL_BSTOPRE from mpc83xx.h,
which has been defined in fsl_ddr_sdram.hSigned-off-by: Shengzhou Liu
24 Jul, 2013
1 commit
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Signed-off-by: Wolfgang Denk
[trini: Fixup common/cmd_io.c]
Signed-off-by: Tom Rini
24 Oct, 2012
2 commits
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This processor, though very similar to other members of the
PowerQUICC II Pro family (namely 8308, 8360 and 832x), provides
yet another feature set than any supported sibling.Signed-off-by: Gerlando Falauto
Signed-off-by: Kim Phillips -
Introduce a new configuration token CONFIG_MPC830x to be shared among
mpc8308 and mpc8309. Define it for existing 8308 boards, and refactor
existing common code so to make future introduction of 8309 simpler.Signed-off-by: Gerlando Falauto
Signed-off-by: Kim Phillips
04 Nov, 2011
3 commits
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Signed-off-by: Joe Hershberger
Cc: Joe Hershberger
Signed-off-by: Kim Phillips -
Signed-off-by: Heiko Schocher
Added its mask, too, for intra-file consistency.
Signed-off-by: Kim Phillips
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Signed-off-by: Heiko Schocher
Signed-off-by: Kim Phillips
07 Jul, 2011
1 commit
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Signed-off-by: Andre Schwarz
Signed-off-by: Kim Phillips
06 Feb, 2011
1 commit
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Use SPMR instead of HRCWL when calculating clocks as HCRWL
may be changed and the CPU will not pick up all changes
until there is a POR. u-boot will think SPMF has changed and get
the clocks wrong.Signed-off-by: Joakim Tjernlund
Signed-off-by: Kim Phillips
24 Sep, 2010
2 commits
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This change lays the groundwork for the BOOTFLAG_* flags being removed.
This change has the small affect of delaying 100ms on PCI initialization
after a warm boot as opposed to the optimal 1ms on some boards.Signed-off-by: Peter Tyser
included the mpc8308_p1m board.
Signed-off-by: Kim Phillips
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This patch adds defines to set supported fields in System I/O
Configuration Registers High and Low on Freescale MPC8308 CPU.Signed-off-by: Ilya Yanok
Signed-off-by: Kim Phillips
10 Jul, 2010
1 commit
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This patch adds basic support for Freescale MPC8308 CPU. Serial ports,
NOR flash and integrated Ethernet controllers are supported.
PCI Express is also supported. eSDHC, NAND and USB may work but aren't
tested (using ULPI PHY requires additional patch).Signed-off-by: Ilya Yanok
Signed-off-by: Kim Phillips
04 Jun, 2010
1 commit
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This patch changed the SICRL_USBDR define to reflect the 4 different bit
settings for this two-bit field. The four different options are '00', '01',
'10', and '11'. This patch also corrects the config file for SIMPC8313 and
MPC8313ERDB for the appropriate fields. This change only affects the MPC8313
cpu.Signed-off-by: Ron Madrid
Signed-off-by: Kim Phillips
22 Aug, 2009
1 commit
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Signed-off-by: Heiko Schocher
Signed-off-by: Kim Phillips
03 Jul, 2009
1 commit
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Signed-off-by: Peter Tyser
Reviewed-by: Ira W. Snyder
Tested-by: Ira W. Snyder
Acked-by: Kim Phillips
Signed-off-by: Kumar Gala
13 Jun, 2009
1 commit
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Use the standard lowercase "x" capitalization that other Freescale
architectures use for CPU defines to prevent confusion and errorsSigned-off-by: Peter Tyser
Signed-off-by: Kim Phillips
17 Feb, 2009
2 commits
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Signed-off-by: Heiko Schocher
Signed-off-by: Kim Phillips -
Signed-off-by: Andy Fleming
22 Jan, 2009
2 commits
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This patch adds support for MPC83xx PCI-E controllers in Root Complex
mode.The patch is based on Tony Li and Dave Liu work[1].
Though unlike the original patch, by default we don't register PCI-E
buses for use in U-Boot, we only configure the controllers for future
use in other OSes (Linux). This is done because we don't have enough
of spare BATs to map all the PCI-E regions.To actually use PCI-E in U-Boot, users should explicitly define
CONFIG_83XX_GENERIC_PCIE_REGISTER_HOSES symbol in the board file. And
only then U-Boot will able to access PCI-E, but at the cost of disabled
address translation.[1] http://lists.denx.de/pipermail/u-boot/2008-January/027630.html
Signed-off-by: Tony Li
Signed-off-by: Anton Vorontsov
Acked-by: Dave Liu
Signed-off-by: Kim Phillips -
When running a system with 2 or more MPC8349EMDS boards in PCI agent mode,
the boards will lock up the PCI bus by scanning against each other.The boards lock against each other by trying to access the PCI bus before
clearing their configuration lock bit. Both boards end up in a loop,
sending and receiving "Target Not Ready" messages forever.When running in PCI agent mode, the scanning now takes place after the
boards have cleared their configuration lock bit.Also, add a missing declaration to the mpc83xx.h header file, fixing a
build warning.Signed-off-by: Ira W. Snyder
Signed-off-by: Kim Phillips
20 Nov, 2008
1 commit
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Signed-off-by: Heiko Schocher
Signed-off-by: Kim Phillips
30 Oct, 2008
1 commit
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- Rename lbus83xx_t to fsl_lbus_t and move it to asm/fsl_lbc.h so that it
can be shared by both 83xx and 85xx
- Remove lbus83xx_t and replace it with fsl_lbus_t in all 83xx boards
files which use lbus83xx_t.
- Move FMR, FIR, FCR, FPAR, LTESR from mpc83xx.h to asm/fsl_lbc.h so that
85xx can share them.Signed-off-by: Jason Jin
Signed-off-by: Haiying Wang
Signed-off-by: Scott Wood
22 Oct, 2008
1 commit
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We'll use these masks to parse TSEC modes out of HRCWH.
Signed-off-by: Anton Vorontsov
Signed-off-by: Kim Phillips
24 Sep, 2008
1 commit
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Fixed typo from CONIFG_MPC837X to CONFIG_MPC837X
Signed-off-by: Nobuhiro Iwamatsu
Signed-off-by: Kim Phillips
26 Aug, 2008
1 commit
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This patch adds elements to the 83xx sysconf structure and #define values that are used
by mpc83xx family devices.Signed-off-by: Nick Spence
Signed-off-by: Kim Phillips
13 Aug, 2008
1 commit
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Note that with older board revisions, NAND boot may only work after a
power-on reset, and not after a warm reset. I don't have a newer board
to test on; if you have a board with a 33MHz crystal, please let me know
if it works after a warm reset.Signed-off-by: Scott Wood
15 Jul, 2008
1 commit
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Delete the crypto node if not on an E-processor. If on 8360 or 834x family,
check rev and up-rev crypto node (to SEC rev. 2.4 property values)
if on an 'EA' processor, e.g. MPC8349EA.Signed-off-by: Kim Phillips
11 Jun, 2008
2 commits
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This patch moves Freescale Localbus defines out of mpc83xx.h, so we could
use it on MPC85xx and MPC86xx processors.Signed-off-by: Anton Vorontsov
Acked-by: Andy Fleming
Signed-off-by: Kim Phillips -
Signed-off-by: Tor Krill
Signed-off-by: Kim Phillips
29 Mar, 2008
1 commit
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in the spirit of commit 1ced121600b2060ab2ff9f0fddd9421fd70a0dc6,
85xx's "Update SVR numbers to expand support", simplify SPRIDR processing
and processor ID display. Add REVID_{MAJ,MIN}OR macros to make
REVID dependent code simpler. Also added PARTID_NO_E and IS_E_PROCESSOR
convenience macros.Signed-off-by: Kim Phillips
26 Mar, 2008
2 commits
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Current DDR setup easily causes memory corruption, this patch fixes it.
Also fix TIMING_CFG0_MRS_CYC definition.
Signed-off-by: Anton Vorontsov
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The following changes are based on kernel UCC ethernet performance:
1. Make the CSB bus pipeline depth as 4, and enable the repeat mode
2. Optimize transactions between QE and CSB. Added CFG_SPCR_OPT
switch to enable this setting.The following changes are based on the App Note AN3369 and
verified to improve memory latency using LMbench:3. CS0_CONFIG[AP_n_EN] is changed from 1 to 0
4. CS0_CONFIG[ODT_WR_CONFIG] set to 1. Was a reserved setting
previously.
5. TIMING_CFG_1[WRREC] is changed from 3clks to 2clks (based on
Twr=15ns, and this was already the setting in DDR_MODE)
6. TIMING_CFG_1[PRETOACT] is changed from 3clks to 2clks. (based on
Trp=15ns)
7. TIMING_CFG_1[ACTTOPRE] is changed from 9clks to 6clks. (based on
Tras=40ns)
8. TIMING_CFG_1[ACTTORW] is changed from 3clks to 2clks. (based on
Trcd=15ns)
9. TIMING_CFG_1[REFREC] changed from 21 clks to 11clks. (based on
Trfc=75ns)
10. TIMING_CFG_2[FOUR_ACT] is changed from 10 clks to 7clks. (based
on Tfaw=50ns)
11. TIMING_CFG_2[ADD_LAT] and DDR_MODE[AL] changed from 0 to 1 (based
on CL=3 and WL=2).Signed-off-by: Michael Barkowski
Acked-by: Kim Phillips
18 Jan, 2008
1 commit
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The commit 9e89647889cd4b5ada5b5e7cad6cbe55737a08d7
will cause the mpc8315erdb board can't boot up.The patch fix that bug, and remove the duplicated #ifdef
CFG_SPCR_TSECEP code and clean the SCCR_TSEC2 for
MPC8313E processor.Signed-off-by: Dave Liu
Signed-off-by: Kim Phillips
17 Jan, 2008
1 commit
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System registers that are modified are the Arbiter Configuration
Register (ACR), the System Priority Control Register (SPCR), and the
System Clock Configuration Register (SCCR).Signed-off by: Michael F. Reiss
Signed-off by: Joe D'Abbraccio
Signed-off-by: Kim Phillips
11 Jan, 2008
2 commits
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According to the latest user manual of MPC8315E,
1) The SVCOD of HRCWL is different than 837x
2) The SCCR has changesSigned-off-by: Dave Liu
Signed-off-by: Kim Phillips -
The SPCR about TSEC priority is wrong.
Signed-off-by: Michael Barkowski
Signed-off-by: Joe D'Abbraccio
Signed-off-by: Dave Liu
Signed-off-by: Kim Phillips
08 Jan, 2008
2 commits
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The MPC8315E SoC including e300c3 core and new IP blocks,
such as TDM, PCI Express and SATA controller.Signed-off-by: Dave Liu
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The MPC837x SoC including e300c4 core and new IP blocks,
such as SDHC, PCI Express and SATA controller.Signed-off-by: Dave Liu
17 Aug, 2007
1 commit
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add board_add_ram_info, to make memory diagnostic output more
consistent. u-boot banner output now looks like:DRAM: 256 MB (DDR1, 64-bit, ECC on)
and for boards with SDRAM on the local bus, a line such as this is
added:SDRAM: 64 MB (local bus)
also replaced some magic numbers with their equivalent define names.
Signed-off-by: Kim Phillips
10 Aug, 2007
1 commit
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Update the cpu_init_f() function in cpu/mpc83xx/cpu_init.c to program the
bitfields for all 83xx processors. The code to update some bitfields was
compiled only on some processors. Now, the bitfields are programmed as long
as the corresponding CFG_SCCR option is defined in the board header file.
This means that the board header file should not define any CFG_SCCR macros
for bitfields that don't exist on that processor, otherwise the SCCR will be
programmed incorrectly.Signed-off-by: Timur Tabi
Signed-off-by: Kim Phillips
