Eric Lee / smarc-uboot

04 Jul, 2011

2 commits

  • 2c451f783   armv7: cache maintenance operations for armv7 ... Browse Code »

    - Add a framework for layered cache maintenance
    - separate out SOC specific outer cache maintenance from
    maintenance of caches known to CPU

    - Add generic ARMv7 cache maintenance operations that affect all
    caches known to ARMv7 CPUs. For instance in Cortex-A8 these
    opertions will affect both L1 and L2 caches. In Cortex-A9
    these will affect only L1 cache

    - D-cache operations supported:
    - Invalidate entire D-cache
    - Invalidate D-cache range
    - Flush(clean & invalidate) entire D-cache
    - Flush D-cache range
    - I-cache operations supported:
    - Invalidate entire I-cache

    - Add maintenance functions for TLB, branch predictor array etc.

    - Enable -march=armv7-a so that armv7 assembly instructions can be
    used

    Signed-off-by: Aneesh V

    Aneesh V
     
  • 4c93da7c3   arm: make default implementation of cache_flush() weakly linked ... Browse Code »

    make default implementation of cache_flush() weakly linked so that
    sub-architectures can override it

    Signed-off-by: Aneesh V

    Aneesh V
     

02 Jul, 2011

7 commits

  • ff6b47ad2   Makefile: need to remove generated u-boot-nand_spl.lds ... Browse Code »

    On MPC85xx based NAND_SPL builds we generate a u-boot-nand_spl.lds based
    on output from preprocessor. We where never removed it.

    Signed-off-by: Kumar Gala
    Signed-off-by: Scott Wood

    Kumar Gala
     
  • eced4626e   NAND: Add 16bit NAND support for the NDFC ... Browse Code »

    This patch adds support for 16 bit NAND devices attached to the
    NDFC on ppc4xx processors. Two config entries were added:

    CONFIG_SYS_NDFC_16 - Setting this tells the NDFC that a
    16 bit device is attached.
    CONFIG_SYS_NDFC_EBC0_CFG - This is for the External Bus
    Controller configuration register.

    Also, a new ndfc_read_byte() function was added which does not
    first convert the data to little endian.

    The NAND SPL was also modified to do 16bit bad block testing
    when a 16 bit chip is being used.

    Signed-off-by: Alex Waterman
    Signed-off-by: Scott Wood

    Alex Waterman
     
  • c9494866d   cmd_nand: add nand write.trimffs command ... Browse Code »
    1

    Add another nand write. variant, trimffs. This command will request of
    nand_write_skip_bad() that all trailing all-0xff pages will be
    dropped from eraseblocks when they are written to flash as-per the
    reccommended behaviour of the UBI FAQ [1].

    The function that implements this timming is the drop_ffs() function
    by Artem Bityutskiy, ported from the mtd-utils tree.

    [1] http://www.linux-mtd.infradead.org/doc/ubi.html#L_flasher_algo

    Signed-off-by: Ben Gardiner
    CC: Artem Bityutskiy
    CC: Detlev Zundel
    Acked-by: Scott Wood
    Signed-off-by: Scott Wood

    Ben Gardiner
     
  • 169d54d8b   nand_util: drop trailing all-0xff pages if requested ... Browse Code »

    Add a flag to nand_read_skip_bad() such that if true, any trailing
    pages in an eraseblock whose contents are entirely 0xff will be
    dropped.

    The implementation is via a new drop_ffs() function which is
    based on the function of the same name from the ubiformat
    utility by Artem Bityutskiy.

    This is as-per the reccomendations of the UBI FAQ [1]

    [1] http://www.linux-mtd.infradead.org/doc/ubi.html#L_flasher_algo

    Signed-off-by: Ben Gardiner
    CC: Artem Bityutskiy
    Acked-by: Detlev Zundel
    CC: Scott Wood
    Signed-off-by: Scott Wood

    Ben Gardiner
     
  • c135456ff   nand_util: treat WITH_YAFFS_OOB as a mode ... Browse Code »

    When specified in the flags argument of nand_write, WITH_YAFFS_OOB causes an
    operation which is mutually exclusive with the 'usual' way of writing.

    Add a check that client code does not specify WITH_YAFFS_OOB along with any
    other flags and add a comment indicating that the WITH_YAFFS_OOB flag should
    not be mixed with other flags.

    Signed-off-by: Ben Gardiner
    CC: Scott Wood
    Signed-off-by: Scott Wood

    Ben Gardiner
     
  • a6c9aa1f9   nand_util: convert nand_write_skip_bad() to flags ... Browse Code »

    In a future commit the behaviour of nand_write_skip_bad()
    will be further extended.

    Convert the only flag currently passed to the nand_write_
    skip_bad() function to a bitfield of only one allocated
    member. This should avoid an explosion of int's at the
    end of the parameter list or the ambiguous calls like

    nand_write_skip_bad(info, offset, len, buf, 0, 1, 1);
    nand_write_skip_bad(info, offset, len, buf, 0, 1, 0);

    Instead there will be:

    nand_write_skip_bad(info, offset, len, buf, WITH_YAFFS_OOB |
    WITH_OTHER);

    Signed-off-by: Ben Gardiner
    Acked-by: Detlev Zundel
    Signed-off-by: Scott Wood

    Ben Gardiner
     
  • bee038e9f   nand_base: trivial: fix comment read/write comment ... Browse Code »

    Replace an incorrect 'read' with 'write' in a comment.

    Signed-off-by: Ben Gardiner
    Acked-by: Detlev Zundel
    Signed-off-by: Scott Wood

    Ben Gardiner
     

01 Jul, 2011

1 commit

30 Jun, 2011

1 commit

29 Jun, 2011

1 commit

  • 4c2105cb9   cfi_flash: reverse geometry for newer STM parts ... Browse Code »

    For newer STM parts where CFI >= 1.1, there is a byte in the extended
    structure that declares the flash layout type (just like the AMD parts),
    so key off of that to find out when we need to reverse the geometry.

    This can be seen with M29W640 parts where U-Boot does:
    Bank # 1: CFI conformant FLASH (16 x 16) Size: 8 MB in 135 Sectors
    AMD Standard command set, Manufacturer ID: 0x20, Device ID: 0x22ED
    Erase timeout: 8192 ms, write timeout: 1 ms
    Buffer write timeout: 1 ms, buffer size: 16 bytes

    Sector Start Addresses:
    20000000 RO 20002000 RO 20004000 RO 20006000 RO 20008000 RO
    2000A000 RO 2000C000 RO 2000E000 RO 20010000 RO 20020000 RO
    ...

    But Linux does:
    physmap platform flash device: 00800000 at 20000000
    physmap-flash.0: Found 1 x16 devices at 0x0 in 16-bit bank.
    Manufacturer ID 0x000020 Chip ID 0x0022ed
    physmap-flash.0: Swapping erase regions for top-boot CFI table.

    Signed-off-by: Mike Frysinger
    Signed-off-by: Stefan Roese

    Mike Frysinger
     

28 Jun, 2011

2 commits

25 Jun, 2011

3 commits

23 Jun, 2011

22 commits

22 Jun, 2011

1 commit