01 Jul, 2022
1 commit
08 Apr, 2021
1 commit
16 Apr, 2020
1 commit
29 Oct, 2019
2 commits
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Optee has 4MB shared memory at its top space which was assigned to
non-secure OS partition in ATF. By default this memory is added to
u-boot DDR banks and will pass to kernel. This means kernel has possibility
to allocate from this memory for system usage. At same time this memory is
used by optee and mem-remapped by optee kernel driver. So it is possible to
have conflict and cause kernel crash.Fix the issue by removing the shared memory from u-boot DDR banks. Then it
is not visible for both u-boot and kernel and can avoid such issue.Signed-off-by: Ye Li
Reviewed-by: Anson Huang
(cherry picked from commit 164279c42de0d058b7abe198cc154ee683087e6a) -
In MLK-22582, write memcmp incorrectly as memcpy.
Signed-off-by: Alice Guo
(cherry picked from commit 16a073f563a25401f1ec289db1c82dd8dab61601)
28 Oct, 2019
5 commits
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Both imx8mn/imx8mm EVK boards have eMMC 5.1 chip and support SD3.0
So we enable the HS400ES and UHS configs to enhance eMMC/SD access.The change also needs to set usdhc clock to 400Mhz and update compatible
string to fsl,imx8mm-usdhcSigned-off-by: Ye Li
Reviewed-by: Peng Fan
(cherry picked from commit cf83fe7dcfcb14dd633ad43ef387793a863e111a) -
iMX8MQ EVK board has a eMMC5.0 chip and supports SD3.0, so enable the UHS
and HS400 configs to enhance the eMMC/SD access.The change also needs to set usdhc clock to 400Mhz, and add the off-on-delay-us
to SD reset pin, otherwise some SD cards will fail to select UHS mode in
re-initialization.Signed-off-by: Ye Li
(cherry picked from commit 57e1bc5f634be231b2bfd10cf0cbbff86dadd2e1) -
The property was changed to "u-boot,off-on-delay-us" in u-boot fixed
regulator. Update the dts to use the new nameSigned-off-by: Ye Li
Reviewed-by: Peng Fan
(cherry picked from commit e68d12af8d17ae1017eacfc73b72ab999ef9837f) -
Verify/dump boot structures.
Signed-off-by: Alice Guo
(cherry picked from commit 65354b516d9919509fadff096c1ba6808e6975cf) -
Verify/dump boot structures written to NAND Flash chip.
Signed-off-by: Alice Guo
(cherry picked from commit 215953009a0429705a3aaaa7c495e6ad7a0a8a3a)
25 Oct, 2019
1 commit
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Move the macro IMX_LOAD_HDMI_FIMRWARE to Kconfig, so it can be enable or
disable in different defconfig.Change-Id: I2e1291d3bc2d6efb29309525b33b84ba8f9b83da
Signed-off-by: Zhang Bo
24 Oct, 2019
2 commits
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Since commit c98b47f1ff60 ("MLK-22749 imx8mq: Add workaround to fix sticky
bits lock up") it's not possible to build i.MX8MM and i.MX8MN targets with
CONFIG_SECURE_BOOT enabled:CC cmd/version.o
arch/arm/mach-imx/imx8m/soc.c:326:23: error: ‘CONFIG_IMX_UNIQUE_ID’ undeclared \
(first use in this function); did you mean ‘CONFIG_IMX_VIDEO_SKIP’?
if (!is_uid_matched(CONFIG_IMX_UNIQUE_ID))
^~~~~~~~~~~~~~~~~~~~The OCOTP sticky bit workaround is only needed for i.MX8MQ devices, other devices
should not build the secure_lockup() function.Add CONFIG_IMX8MQ to the conditional compilation to avoid such issue.
Fixes: c98b47f1ff60 ("MLK-22749 imx8mq: Add workaround to fix sticky bits lock up")
Signed-off-by: Breno Lima
Reviewed-by: Ye Li
(cherry picked from commit be033bff3c718e8bd7d4ac5ecfe4361892fc6e61) -
add the missing bch register debug0
Signed-off-by: Han Xu
(cherry picked from commit 0883946855f7e1eabe26787fbc8529ac412047e7)
15 Oct, 2019
4 commits
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Latest SCFW has removed old MISC SECO commands. So update the codes
to use new SECO commands.Signed-off-by: Ye Li
Reviewed-by: Peng Fan
(cherry picked from commit 8e54efce6d2a1691605ae23983ff91f4a702adba) -
Current codes have wrong definitions for SC_MISC_SECO_AUTH_SECO_FW,
SC_MISC_SECO_AUTH_HDMI_TX_FW and SC_MISC_SECO_AUTH_HDMI_RX_FW and
cause HDP firmware authentication failed.Sync the API definitions with latest SCFW export.
Signed-off-by: Ye Li
(cherry picked from commit 87ee3c16a649a418b8c6fdae53234f88a90c8fb3) -
flash in u-boot for imx8mm-evk
imx8mm-evk uses BCH encoding and randomizer
modify macro and print size_t with %zx
use CONFIG_IMX8M because it should apply to imx8mq/mm/mn
Signed-off-by: Alice Guo
(cherry picked from commit 8d95b51fd70be29ef6beaa0f65c101b329f04f8e) -
dependency of CMD_NANDBCB`s default value
compiling nandbcb of imx8mm-evk depends on NAND and CMD_MTDPARTS
modify dependency of CMD_NANDBCB`s default value
Signed-off-by: Alice Guo
(cherry picked from commit 1b14e8cbefdb0f8126ceb6a85b1fd0db142328e6)
12 Oct, 2019
1 commit
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Currently is not possible to use dek_blob command in
mx8mq:u-boot=> dek_blob 0x40400000 0x40401000 128
Cannot get OP-TEE deviceAdd OP-TEE Device Tree Bindings to fix this issue.
Reviewed-by: Ye Li
Signed-off-by: Clement Faure
Signed-off-by: Breno Lima
(cherry picked from commit f762fe218ec60025e2dfd6173efaa826286ba297)
11 Oct, 2019
5 commits
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Current flexspi driver enables the Quad DTR read, so the measured
100Mhz SCLK is actually for DTR mode not SDR. However, according to
MT25QU256ABA datasheet, this flash only supports max DTR at 90Mhz and
max SDR at 166Mhz. It means current clock setting violate the flash
spec. So change back the flexspi clock to align with imx8mm.Signed-off-by: Ye Li
Reviewed-by: Peng Fan
(cherry picked from commit 3bf41bae974003550b70ea1a8b44ccb3117d818f)
(cherry picked from commit 4a369b527c3842751a4edf0171562a0e40c331ba) -
On B1 chips with HAB v4.4, the sticky bits are not locked up in
HAB closed mode. We introduce a workaround in SPL to lock up
these bits and clear Manufacturing Protection Private Key for
secure boot.For field return case, user has to build a SPL with
CONFIG_SECURE_STICKY_BITS_LOCKUP=n and set CONFIG_IMX_UNIQUE_ID to
part's unique id. When the UID check is passed, sticky bits are not
lockup and users can burn field return fuse. Otherwise the boot will
stop.Signed-off-by: Ye Li
(cherry picked from commit c98b47f1ff60e1f99807e24fd76053ad880f803e) -
Add REVC informaiton.
Signed-off-by: Frank Li
(cherry picked from commit c7231f2c7a5c1dc754b5fb9bf05941141877a0ec)
(cherry picked from commit 9a33170a4f4ff2ad2ab0d87e74e722a0e833abaa) -
bchtype in FCB should be associated to the gf_13/14 settings in BCH, fix
the issue and test on Micron 29F64G08CBABB, it can boot after the
change.Signed-off-by: Han Xu
(cherry picked from commit 9cc7bf9b17565b4e0d73acd690e32394034dfae2) -
gf_13/14 mask was not set correctly in register definition.
Signed-off-by: Han Xu
(cherry picked from commit b8aed98b2ecfb0def64c474e1ae171930da4c9fc)
29 Sep, 2019
6 commits
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ROM SError happens on two cases:
1. ERR050342, on iMX8MQ HDCP enabled parts ROM writes to GPV1 register, but
when ROM patch lock is fused, this write will cause SError.2. ERR050350, on iMX8MQ/MM/MN, when the field return fuse is burned, HAB
is field return mode, but the last 4K of ROM is still protected and cause SError.Since ROM mask SError until ATF unmask it, so then ATF always meets the exception.
This patch works around the issue in SPL by enabling SPL Exception vectors table
and the SError exception, take the exception to eret immediately to clear the SError.Signed-off-by: Ye Li
Reviewed-by: Peng Fan
(cherry picked from commit f05dd45251ca82cc54e13a616f00744c26faab53)
(cherry picked from commit 25d059411e702a4002f1aa157839001f796dd9f6) -
Sometimes we met SERROR, but only to catch it when Linux boots up.
Let's enable catching in U-Boot to catch it ealier and ease debug.Signed-off-by: Peng Fan
(cherry picked from commit 7a0c9b08886e5dc7d50e640ed56eed0fe612161f)
(cherry picked from commit 33da22c4793e56077033a4f6c567894badb8e907)
(cherry picked from commit 4da3e872b7c61b93fa227935a7b45eb5fcb252e1) -
Add subcommand for add writing BCB only, where we provide appropriate
offsets for firmware1 and firmware2 and size.Example of usage:
> nandbcb bcbonly 0x00180000 0x00080000 0x00200000
Writing 1024 bytes to 0x0: randomizing
OK
Writing 1024 bytes to 0x20000: randomizing
OKSigned-off-by: Igor Opaniuk
(cherry picked from commit 353a38576ed6f21431bf499a4b402a5ca571f0fa) -
Move code for writing FCB/DBBT pages to a separate function
Signed-off-by: Igor Opaniuk
(cherry picked from commit c4e8b725681c9e7d18845260ac1061aedb9166a4) -
Add support for updating FCB/DBBT on i.MX7:
- additional new fields in FCB structure
- Leverage hardware BCH/randomizer for writing FCBSigned-off-by: Igor Opaniuk
Signed-off-by: Alice Guo
(cherry picked from commit b4b3049b1e4a069e522a1112bf4f9e0253836b2d) -
Extend GPMI Integrated ECC Control Register Description, include
additional defines for enabling randomizer function and providing
proper randomizer type.For additional details check i.MX7 APR, section
9.6.6.3 GPMI Integrated ECC Control Register Description
(GPMI_ECCCTRLn)Signed-off-by: Igor Opaniuk
(cherry picked from commit 212ab2205175b9be726ef6c00f523391882a7824)
23 Sep, 2019
1 commit
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Update the mx7ulp wdog disable sequence to avoid potential reset issue
in unlock or refresh sequence. Both sequence need two words write
to wdog CNT register in 16 bus clocks window, if miss the window,
the write will cause violation in wdog and reset the chip.Current u-boot code is using writel() function which has a DMB barrier
to order the memory access. The DMB between two words write may introduce
some delay in certain circumstance, causing the wdog reset due to 16 bus
clock window requirement.This patch replaces writel() function by __raw_writel() to avoid such issue,
and improve to check if watchdog is already disabled or unlocked.Signed-off-by: Ye Li
Tested-by: Breno Lima
Reviewed-by: Peng Fan
(cherry picked from commit b8c99d5f5bcc5573d3394b68890db16b6bb5fc88)
11 Sep, 2019
2 commits
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When enable u-boot splash screen and set kernel dtb with -hdmi.dtb on
imx8qm, the kernel reboot (partition reboot) will hang in u-boot if HDMI
cable is plugged in.
The root cause is kernel set the clock source of DC0 display0 channel to
bypass clock, when doing reboot this clock setting may not be cleared. So
u-boot has wrong clock source and cause lpcg stop bit always set.Fix the issue by adding the clock parent setting and not depend on default
parent value.Signed-off-by: Ye Li
Reviewed-by: Peng Fan
(cherry picked from commit 104c4b5cdc83fb671c6474708bdd00c2dfb01113)
(cherry picked from commit 8a287c629018e6bf647c3c617fca3e6c94a3d2a4) -
Have missed the lpcg settings when porting to 2019.04 u-boot
Signed-off-by: Ye Li
Reviewed-by: Peng Fan
(cherry picked from commit 4096d7806a0dcc501123c8c2cdf734620e37d169)
30 Aug, 2019
2 commits
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The dash-linux tree has dropped pd tree, so we could not get the reg.
The power-doamins property has a cell indicating the resource id,
let's use it for sid programming.Signed-off-by: Peng Fan
Reviewed-by: Ye Li -
Upstream kernel refactors the power domain nodes and the usage of
power-domains property in DTB. So when checking available resources
in AP partition with this kernel DTB, u-boot will reports some
warnings.
This patch will support both two power domain designs during updating
kernel DTB.Signed-off-by: Ye Li
Reviewed-by: Peng Fan
12 Aug, 2019
1 commit
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Like iMX8MM, iMX8MN also needs SW to load TMU TASR and TCALIV registers
value from fuse before enabling TMU calibration. Otherwise the calibration
is not exact.Signed-off-by: Ye Li
Reviewed-by: Anson Huang
(cherry picked from commit 9fb7f904ff6a03e2951a770daba12a522373c8ae)
09 Aug, 2019
5 commits
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Add pci0 alias and gpr property for pcie node.
Signed-off-by: Ye Li
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Add pci0 alias and gpr property for pcie node, and fix its reset-gpio
polarity.Signed-off-by: Ye Li
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Add pci alias for pcieb.
Enable the pcieb node in MEK board and add relevant pin config and
regulator.Signed-off-by: Ye Li
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Add PCI alias for pciea and pcieb.
Enable the pciea node in MEK board and add relevant pin config and
regulatorSigned-off-by: Ye Li
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The DM iMX PCI driver has DM_FLAG_OS_PREPARE set and will call
imx_pcie_remove() from the .remove callback. Do not call it from
the architecture code again.Signed-off-by: Marek Vasut
Cc: Bin Meng
Cc: Fabio Estevam
Cc: Stefano Babic
Reviewed-by: Bin Meng
(cherry picked from commit 42dc1230cdec48d0278dcc683bc14527cbea12c5)
