08 Jun, 2014
1 commit
07 Jun, 2014
12 commits
-
Add a driver for the TPS65218 PMIC which is used by TI AM43xx SoCs and
may be used by TI AM335x SoCs.Signed-off-by: Tom Rini
-
The patch populates the slave data which will be used by flash driver to
set the flash quad enable bit.Signed-off-by: Sourav Poddar
-
This patch add support for BCH16_ECC to omap_gpmc driver.
*need to BCH16 ECC scheme*
With newer SLC Flash technologies and MLC NAND, and large densities, pagesizes
Flash devices have become more suspectible to bit-flips. Thus stronger
ECC schemes are required for protecting the data.
But stronger ECC schemes have come with larger-sized ECC syndromes which require
more space in OOB/Spare. This puts constrains like;
(a) BCH16_ECC can correct 16 bit-flips per 512Bytes of data.
(b) BCH16_ECC generates 26-bytes of ECC syndrome / 512B.
Due to (b) this scheme can only be used with NAND devices which have enough
OOB to satisfy following equation:
OOBsize per page >= 26 * (page-size / 512)Signed-off-by: Pekon Gupta
-
GPMC controller needs to be configured based on bus-width of the NAND device
connected to it. Also, dynamic detection of NAND bus-width from on-chip ONFI
parameters is not possible in following situations:
SPL: SPL NAND drivers does not support ONFI parameter reading.
U-boot: GPMC controller iniitalization is done in omap_gpmc.c:board_nand_init()
which is called before probing for devices, hence any ONFI parameter
information is not available during GPMC initialization.Thus, OMAP NAND driver expected board developers to explicitely write GPMC
configurations specific to NAND device attached on board in board files itself.
But this was troublesome for board manufacturers as they need to dive into
lengthy platform & SoC documents to find details of GPMC registers and
appropriate configurations to get NAND device working.This patch instead adds existing CONFIG_SYS_NAND_BUSWIDTH_16BIT to board config
hich indicates that connected NAND device has x16 bus-width. And then based on
this config GPMC driver itself initializes itself based on NAND bus-width. This
keeps board developers free from knowing GPMC controller specific internals.Signed-off-by: Pekon Gupta
-
As per following Sections in ONFI Spec, NAND_CMD_READID should use only
lower 8-bit for transfering command, address and data even on x16 NAND device.*Section: Target Initialization"
"The Read ID and Read Parameter Page commands only use the lower 8-bits of the
data bus. The host shall not issue commands that use a word data width on x16
devices until the host determines the device supports a 16-bit data bus width
in the parameter page."*Section: Bus Width Requirements*
"When the host supports a 16-bit bus width, only data is transferred at the
16-bit width. All address and command line transfers shall use only the lower
8-bits of the data bus. During command transfers, the host may place any value
on the upper 8-bits of the data bus. During address transfers, the host shall
set the upper 8-bits of the data bus to 00h."Thus porting following commit from linux-kernel to ensure that column address
is not altered to align to x16 bus when issuing NAND_CMD_READID command.commit 3dad2344e92c6e1aeae42df1c4824f307c51bcc7
mtd: nand: force NAND_CMD_READID onto 8-bit bus
Author: Brian Norris (preserving authorship)The NAND command helpers tend to automatically shift the column address
for x16 bus devices, since most commands expect a word address, not a
byte address. The Read ID command, however, expects an 8-bit address
(i.e., 0x00, 0x20, or 0x40 should not be translated to 0x00, 0x10, or
0x20).This fixes the column address for a few drivers which imitate the
nand_base defaults.Signed-off-by: Pekon Gupta
-
Porting below commit from linux-tree, preserving original authorship & commit log
commit bd9c6e99b58255b9de1982711ac9487c9a2f18be
Author: Brian Norris
mtd: nand: don't use read_buf for 8-bit ONFI transfersUse a repeated read_byte() instead of read_buf(), since for x16 buswidth
devices, we need to avoid the upper I/O[16:9] bits. See the following
commit for reference:commit 05f7835975dad6b3b517f9e23415985e648fb875 (from linux-tree)
Author: Uwe Kleine-König
Date: Thu Dec 5 22:22:04 2013 +0100mtd: nand: don't use {read,write}_buf for 8-bit transfers
Now, I think that all barriers to probing ONFI on x16 devices are
removed, so remove the check from nand_flash_detect_onfi().Signed-off-by: Pekon Gupta
-
This patch
omap-elm.c: replaces -ve integer value returned during errorneous condition,
with proper error-codes.
omap-gpmc.c: updates omap-gpmc driver to pass error-codes returned from
omap-elm driver to upper layersSigned-off-by: Pekon Gupta
Reviewed-by: Stefan Roese -
This patch tries to avoid some local pointer dereferences, by using common
local variables in omap_correct_data_bch()Signed-off-by: Pekon Gupta
Reviewed-by: Stefan Roese -
This patch renames 'struct nand_bch_priv' which currently holds private data only
for BCH ECC schemes, into 'struct omap_nand_info' so that same can be used for
all ECC schemesSigned-off-by: Pekon Gupta
Reviewed-by: Stefan Roese -
This patch prepares to refactor 'struct nand_bch_priv' -> 'struct omap_nand_info'
And thus performs following clean-ups:
- remove nand_bch_priv.type: use nand_bch_priv.ecc_scheme instead
- remove nand_bch_priv.mode:Signed-off-by: Pekon Gupta
Reviewed-by: Stefan Roese -
ELM hardware engine support ECC error detection for multiple ECC strengths like
+------+------------------------+
|Type | ECC syndrome length |
+------+------------------------+
|BCH4 | 6.5 bytes = 13 nibbles |
|BCH8 | 13 byte = 26 nibbles |
|BCH16 | 26 bytes = 52 nibbles |
+------+------------------------+Current implementation of omap_elm driver uses ECC syndrom length (in 'nibbles')
to differentiate between BCH4/BCH8/BCH16. This patch replaces it with 'bch_type'Signed-off-by: Pekon Gupta
Reviewed-by: Stefan Roese -
There is no dependency of omap_elm.c on omap_gpmc.h
Signed-off-by: Pekon Gupta
Reviewed-by: Stefan Roese
06 Jun, 2014
5 commits
-
The offset of module information is at 128, different from DDR3.
Signed-off-by: York Sun
-
When the DDR controller is initialized below a junction temperature of
0°C and then operated above a junction temperature of 65°C, the DDR
controller may cause receive data errors, resulting ECC errors and/or
corrupted data. This erratum applies to the following SoCs and their
variants: MPC8536, MPC8569, MPC8572, P1010, P1020, P1021, P1022, P1023,
P2020.Signed-off-by: York Sun
-
Replace 80 mircoseconds delay with polling flag ESPI_EV_TXE.
Signed-off-by: Hou Zhiqiang
Reviewed-by: York Sun -
get_phy_id returns -EIO when it can't read from a phy at a given addr. This would cause
create_phy_by_mask to return prematurely before it had tested the other addresses in the provided mask.Example usage:
Replace
phydev = phy_connect(bus, phy_addr, dev, phy_if)
with
phydev = phy_find_by_mask(bus, phy_mask, phy_if)
if (phydev)
phy_connect_dev(phydev, dev);Signed-off-by: Cormier, Jonathan
Cc: Joe Hershberger
02 Jun, 2014
1 commit
30 May, 2014
3 commits
-
This makes it clear where the code resides.
Signed-off-by: Simon Glass
-
Move the CLI prototypes from common.h to cli.h as part of an effort to
reduce the size of common.h.Signed-off-by: Simon Glass
28 May, 2014
4 commits
-
The current pmic i2c code assumes the current i2c bus is
the same as the pmic device's bus. There is nothing ensuring
that to be true. Therefore, select the proper bus before performing
a transaction.Signed-off-by: Aaron Durbin
Signed-off-by: Simon Glass
Acked-by: Heiko Schocher
Reviewed-by: Simon Glass
Signed-off-by: Minkyu Kang -
This adds driver support for the TPS65090 PMU. Support includes
hooking into the pmic infrastructure so that the pmic commands
can be used on the console. The TPS65090 supports the following
functionality:- fet enable/disable/querying
- getting and setting of charge stateEven though it is connected to the pmic infrastructure it does
not hook into the pmic charging charging infrastructure.The device tree binding is from Linux, but only a small subset of
functionality is supported.Signed-off-by: Tom Wai-Hong Tam
Signed-off-by: Hatim Ali
Signed-off-by: Katie Roberts-Hoffman
Signed-off-by: Rong Chang
Signed-off-by: Sean Paul
Signed-off-by: Vincent Palatin
Signed-off-by: Aaron Durbin
Signed-off-by: Simon Glass
Signed-off-by: Minkyu Kang -
This enum should be common across all PMICs rather than having it
independently defined with the same name in multiple places.Signed-off-by: Simon Glass
Signed-off-by: Minkyu Kang -
Commit be3b51aa did this mostly, but several have been added since. Do the
job again.Signed-off-by: Simon Glass
Acked-by: Lukasz Majewski
Signed-off-by: Minkyu Kang
27 May, 2014
3 commits
-
using UBI and DM together leads in compiler error, as
both define a "struct device", so rename "struct device"
in include/dm/device.h to "struct udevice", as we use
linux code (MTD/UBI/UBIFS some USB code,...) and cannot
change the linux "struct device"Signed-off-by: Heiko Schocher
Cc: Simon Glass
Cc: Marek Vasut -
Signed-off-by: Josh Wu
[fix checkpatch line length warning]
Signed-off-by: Andreas Bießmann -
We need check the NULL pointer as at91_pio_get_port() may return NULL.
Also print a error message when at91_pio_get_port() failed otherwise we
cannot notice the failure.Signed-off-by: Josh Wu
Signed-off-by: Andreas Bießmann
25 May, 2014
5 commits
-
The correct value for this setting can vary across SoCs and boards, so make it
configurable.Also reduce the default value to 8, which is the same default as used in the
Linux driver.Signed-off-by: Ian Campbell
Cc: Alexey Brodkin -
On Thu, 2014-05-08 at 22:26 +0100, Ian Campbell wrote:
> The {r,t}xbuffs fields also need to be aligned. Previously this was done
> implicitly because they immediately followed the descriptor tables. Make this
> explicit and also move to the head of the struct.Looks like I managed to not actually commit the move of the field to the
head of the struct! v3.1 follows....Ian.
8From 2937ba01841887317f6792709ed57cb86b5fc0cd Mon Sep 17 00:00:00 2001
From: Ian Campbell
Date: Thu, 1 May 2014 19:45:15 +0100
Subject: [PATCH] net/designware: reorder struct dw_eth_dev to pack more
efficiently.The {tx,rx}_mac_descrtable fields are aligned to ARCH_DMA_MINALIGN, which could
be 256 or even larger. That means there is a potentially huge hole in the
struct before those fields, so move them to the front where they are better
packed.Moving them to the front also helps ensure that so long as dw_eth_dev is
properly aligned (which it is since "net/designware: ensure device private data
is DMA aligned.") the {tx,rx}_mac_descrtable will be too, or at least avoids
having to worry too much about compiler specifics.The {r,t}xbuffs fields also need to be aligned. Previously this was done
implicitly because they immediately followed the descriptor tables. Make this
explicit and also move to the head of the struct.Signed-off-by: Ian Campbell
Cc: Alexey Brodkin
Tested-by: Siarhei Siamashka
Reviewed-by: Siarhei Siamashka -
This is required at least on ARM.
When sending instead of simply invalidating the entire descriptor, flush
as little as possible while still respecting ARCH_DMA_MINALIGN, as
requested by Alexey.Signed-off-by: Ian Campbell
Cc: Alexey Brodkin -
struct dw_eth_dev contains fields which are accessed via DMA, so make sure it
is aligned to a dma boundary. Without this I see:
ERROR: v7_dcache_inval_range - start address is not aligned - 0x7fb677e0Signed-off-by: Ian Campbell
Reviewed-by: Alexey Brodkin
Acked-by: Marek Vasut -
On Mon, 2014-05-05 at 14:18 +0200, Stefan Roese wrote:
> > + case 1:
> > +#if CONFIG_MMC1_PG> Are you sure that this is correct and shouldn't be:
>
> +#ifdef CONFIG_MMC1_PG
>
> ?It's "correct" in so far as it works (the boards.cfg config stuff
#defines things to 1), but I think you are right that it isn't the
preferred style. But...> A quick scan through this patch series shows that this define
> is not set at all. Perhaps its outdated? Or is it used to support
> some other sunxi SoC? Not sure, perhaps it should be removed for
> now....I had thought that it was to support some other board which wasn't
being upstreamed right now, so eventually useful and harmless for now,
but I've just checked and it isn't actually used by any of the boards in
u-boot-sunxi.git. So rather than fix it to use #ifdef lets drop it.
Rather than resend the entire series, here is v5.1 of this patch.> Other than this please add my:
>
> Reviewed-by: Stefan RoeseThanks!
8From 20704e35a41664de5f516ed0e02981ac06085102 Mon Sep 17 00:00:00 2001
From: Ian Campbell
Date: Fri, 7 Mar 2014 04:29:39 +0000
Subject: [PATCH v5.1 7/8] sunxi: mmc supportThis adds support for the MMC controller on the Allwinner A20 (sun7i)
processor.Signed-off-by: Henrik Nordstrom
Signed-off-by: Luke Leighton
Signed-off-by: Oliver Schinagl
Signed-off-by: Wills Wang
Signed-off-by: Ian Campbell
Reviewed-by: Marek Vasut
Reviewed-by: Stefan Roese
Cc: Tom Cubie
Cc: Aaron Maoye
Cc: Pantelis Antoniou
Reviewed-by: Tom Rini
24 May, 2014
1 commit
23 May, 2014
5 commits
-
In 7168977 we made calls to check_and_invalidate_dcache_range()
conditional on !CONFIG_SYS_FSL_ESDHC_USE_PIO. Only define this function
in this case as well.Signed-off-by: Tom Rini
-
This enables specifying which eMMC HW partition to target for any U-Boot
command that uses the generic get_partition() function to parse its
command-line arguments.Acked-by: Pantelis Antoniou
Signed-off-by: Stephen Warren -
This patch adds functions for read, write and authentication
key programming for the Replay Protected Memory Block partition
in the eMMC.Acked-by: Pantelis Antoniou
Signed-off-by: Pierre Aubert -
MMC switch command for unsupported feature (e.g. bus width) sets a switch
error bit in card status. This bit should be checked, and, if it's set,
no access with new controller settings should be performed.Acked-by: Pantelis Antoniou
Signed-off-by: Andrew Gabbasov
