06 Oct, 2014

3 commits

• 5d8ad0cd3   arm: socfpga: clock: Trim down code duplication ... Browse Code »

  Pull out functions to read frequency of Main clock VCO and
  PLL clock VCO as the code is duplicated multiple times.

  Signed-off-by: Marek Vasut
  Cc: Chin Liang See
  Cc: Dinh Nguyen
  Cc: Albert Aribaud
  Cc: Tom Rini
  Cc: Wolfgang Denk
  Cc: Pavel Machek
  Acked-by: Dinh Nguyen
  Acked-by: Pavel Machek

  Marek Vasut

  2014-10-06 23:46:49 +0800  
• a832ddba5   arm: socfpga: clock: Add code to read clock configuration ... Browse Code »

  Add the entire bulk of code to read out clock configuration from the SoCFPGA
  CPU registers. This is important for MMC, QSPI and UART drivers as otherwise
  they cannot determine the frequency of their upstream clock.

  Signed-off-by: Pavel Machek
  Signed-off-by: Marek Vasut
  Cc: Chin Liang See
  Cc: Dinh Nguyen
  Cc: Albert Aribaud
  Cc: Tom Rini
  Cc: Wolfgang Denk
  Cc: Pavel Machek

  V2: Fixed the L4 MP clock divider and synced the clock code with latest
  rocketboards codebase (thanks Dinh for pointing this out)

  Pavel Machek

  2014-10-06 23:46:49 +0800  
• 4425e6285   arm: socfpga: clock: Drop nonsense inlining from clock manager code ... Browse Code »

  The inlining is done by GCC when needed, there is no need to do it
  explicitly. Furthermore, the inline keyword does not force-inline
  the code, but is only a hint for the compiler. Scrub this hint.

  Signed-off-by: Marek Vasut
  Cc: Chin Liang See
  Cc: Dinh Nguyen
  Cc: Albert Aribaud
  Cc: Tom Rini
  Cc: Wolfgang Denk
  Cc: Pavel Machek
  Acked-by: Dinh Nguyen
  Acked-by: Pavel Machek

  Marek Vasut

  2014-10-06 23:46:48 +0800  

30 Aug, 2014

2 commits

• 3ab019e1d   socfpga: Fix SOCFPGA build error for Altera dev kit ... Browse Code »

  To fix the build error when build for Altera dev kit, not
  virtual target. At same time, set the build for Altera dev
  kit as default instead virtual target. With that, U-Boot
  is booting well and SPL still lack of few drivers.

  Signed-off-by: Chin Liang See
  Cc: Pavel Machek
  Cc: Marek Vasut
  Cc: Tom Rini
  Cc: Albert Aribaud

  Chin Liang See

  2014-08-30 03:50:54 +0800  
• 51fb455f8   socfpga: fix clock manager register definition ... Browse Code »

  Structure defining clock manager hardware was wrong, leading to
  wrong registers being accessed and hang in MMC init.

  This fixes structure to match hardware.

  Signed-off-by: Pavel Machek

  Pavel Machek

  2014-08-30 03:50:50 +0800  

07 Apr, 2014

1 commit

• ddfeb0aaf   socfpga: Adding Clock Manager driver ... Browse Code »

  Clock Manager driver will be called to reconfigure all the
  clocks setting based on user input. The input are passed to
  Preloader through handoff files

  Signed-off-by: Chin Liang See
  Cc: Albert Aribaud
  Cc: Tom Rini
  Cc: Wolfgang Denk
  CC: Pavel Machek
  Cc: Dinh Nguyen
  Acked-by: Pavel Machek

  Chin Liang See

  2014-04-07 16:41:50 +0800