01 Sep, 2015
1 commit
31 Aug, 2015
12 commits
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If board uses downstream Chrome OS U-Boot as first stage
bootloader and upstream version is chained second stage,
1.1V is minimum voltage borderline.Signed-off-by: Misha Komarovskiy
Acked-by: Simon Glass -
The boards are sorted by SoC, move the Mele_A1000G_quad entry to the list
of sun6i boards where it belongs.Signed-off-by: Hans de Goede
Acked-by: Ian Campbell -
Signed-off-by: Marcus Cooper
Acked-by: Hans de Goede
Signed-off-by: Hans de Goede -
The inet98v_rev2 is a pcb used in generic A13 based tablets. It features
volume buttons, a power barrel, micro-usb otg, headphone connector and
a power button.The dts file is identical to the one submitted to the upstream kernel.
Signed-off-by: Hans de Goede
Acked-by: Ian Campbell -
The inet97fv2 is a board found in the first generation of cheap allwinner
A10 based 7" tablets.Note that this patch does not add a dts file as we already have one from
our dts syncs with the kernel.Signed-off-by: Hans de Goede
Acked-by: Ian Campbell -
We eventually want to add full nand support, since it makes no sense
to build SPL with nand support and u-boot without, or the other way
around, a single option will suffice.Renaming the Kconfig option now makes things easier when we add full
nand support in the future.The "obj-$(CONFIG_NAND_SUNXI) += sunxi_nand_spl.o" is moved to an
"ifdef CONFIG_SPL_BUILD" block in the Makefile.Signed-off-by: Hans de Goede
Acked-by: Ian Campbell -
Other then having a few less chip-select lines the nand controller
on sun4i, sun5i and sun7i is identical.Note this patch also muxes GPC7 to the NAND on sun7i where as before
it was not muxed this way. GPC7 is a standard NAND pin, so it should
always be muxed to the NAND when in use.Signed-off-by: Hans de Goede
Acked-by: Ian Campbell -
We use DMA for nand data transfers in the SPL, so make sure the DMA
controller is enabled.Signed-off-by: Hans de Goede
Acked-by: Ian Campbell -
Use SYS_NAND_SELF_INIT and only setup the pinmux and clocks when we are
actually using the nand.Signed-off-by: Hans de Goede
Acked-by: Ian Campbell -
With the unified / cleaned up default display output selection changes,
which were done as part of adding composite video out support, our
example LCD_MODE line in the A13-OLinuxIno defconfigs causes the display
code to setup a LCD console by default, rather then a VGA console.Given that the LCD console is only useful for people who have hooked up
the exact lcd-panel from the config, while most people will not have any
lcd panel connected to these boards, this is not a good default.Dropping the LCD_MODE line which was intended as an example fixes this,
instead add a link to the LCD_MODE help text pointing to
http://linux-sunxi.org/LCD which contains the removed and other example
modes.Signed-off-by: Hans de Goede
Acked-by: Ian Campbell -
The gt90h is a pcb found in generic 9" tablets with an A23 soc, 1G RAM
and 8G nand, rtl8723as usb wifi, 1 micro usb port and 1 micro sd slot.The pmic setup on this board is somewhat special, dcdc2 MUST be set
to 1.1V instead of the usual 1.2V otherwise the board is very unstable.
aldo1 is used to power the micro sd slot, dldo1 is used for wifi.This commit adds a defconfig + dts (as submitted to the kernel) for
the gt90h-v4 pcb.Signed-off-by: Hans de Goede
Acked-by: Ian Campbell -
Allow specifying the axp221 dcdc2 voltage via Kconfig, this is necessary
because on some boards the 1.2V default does not work reliable.Signed-off-by: Hans de Goede
Acked-by: Ian Campbell
29 Aug, 2015
12 commits
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invoke enable_usb_clocks during board_usb_init and disable_usb_clocks
during board_usb_exit to enable and disable clocks respectively.Signed-off-by: Kishon Vijay Abraham I
Reviewed-by: Tom Rini -
Implemented board_usb_init(), board_usb_cleanup() and
usb_gadget_handle_interrupts() in omap5 board file that
can be invoked by various gadget drivers.Signed-off-by: Kishon Vijay Abraham I
Reviewed-by: Tom Rini -
Implemented board_usb_init(), board_usb_cleanup() and
usb_gadget_handle_interrupts() in beagle_x15 board file that
can be invoked by various gadget drivers.Signed-off-by: Kishon Vijay Abraham I
Reviewed-by: Tom Rini -
vbus_id_status is initialized in board_usb_init. So remove it
while creating dwc3_device objects.Signed-off-by: Kishon Vijay Abraham I
Reviewed-by: Tom Rini -
This fixes the following genboardscfg.py warnings:
---88---
Signed-off-by: Andreas Bießmann
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This fixes following genboardscfg.py warning:
---88---
Signed-off-by: Andreas Bießmann
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Booting SPEAr600 eval board doesn't work with current mainline U-Boot. With
this patch the low-vector bit is left to '0'. Resulting in the common
relocation of the vectors to 0 (SDRAM) to work correctly.Tested on the SPEAr600 EVB.
Signed-off-by: Stefan Roese
Acked-by: Viresh Kumar
Cc: Vipin Kumar -
ARM supported speeds and init value of core_pll for SDP1200
are programmed wrong as part for the device speed cleanups.
Fixing it here.
Thanks to "Vitaly Andrianov " for bisecting this issueFixes: c37ed9f11b61 ("ARM: keystone2: Fix dev and arm speed detection")
Tested-by: Vitaly Andrianov
Signed-off-by: Lokesh Vutla -
Update README to include uart boot mode support and makefile
changes.Signed-off-by: Lokesh Vutla
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NAND boot mode, ROM expects an image with a gp header in the
beginning and an 8bytes filled with zeros at the end. The same is
true for SD boot on K2G platforms but the file name should be MLO.Renaming u-boot-nand.gph to MLO, so that same image can be used for
NAND and SD boots. And also not including all the u-boot only images
under CONFIG_SPL_BUILD.Reported-by: Nishanth Menon
Reviewed-by: Nishanth Menon
Signed-off-by: Lokesh Vutla -
DP83865 ethernet phy used on DRA74x-evm is quirky and the datasheet
provided IODELAY values for standard RGMII phys do not work.Silicon Revision(SR) 2.0 provides an alternative bit configuration
that allows us to do a "gross adjustment" to launch the data off a
different internal clock edge. Manual IO Delay overrides are still
necessary to fine tune the clock-to-data delays. This is a necessary
workaround for the quirky ethernet Phy we have on the platform.NOTE: SMA registers are spare "kitchen sink" registers that does
contain bits for other workaround as necessary as well. Hence the
control for the same is introduced in a generic SoC specific, board
generic location.Signed-off-by: Nishanth Menon
Reviewed-by: Tom Rini -
Silicon revision 2.0 has new signal routing hence has an updated set of
iodelay parameters to be used. Update the configuration for the same.
Padmux remains the same.Based on data from VayuES2_EVM_Base_Config-20150807.
NOTE: With respect to the RGMII values, the Manual IODelay values
are used for the fine adjusments needed to meet the tight RGMII
specification.Signed-off-by: Nishanth Menon
Reviewed-by: Tom Rini
28 Aug, 2015
2 commits
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Remove ag101 and ag102 support
Signed-off-by: Kun-Hua Huang
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Add nds32 ag101p generic board support.
Signed-off-by: Kun-Hua Huang
26 Aug, 2015
1 commit
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So far we only enabled one legacy serial port on the SMSC LPC47m
superio chipset on Intel Crown Bay board. As the board also has
dual PS/2 ports routed out, enable the keyboard controller which
is i8042 compatible so that we can use PS/2 keyboard and mouse.In order to make PS/2 keyboard work with the VGA console, remove
CONFIG_VGA_AS_SINGLE_DEVICE. To boot Linux kernel with PIC mode
using PIRQ routing table, adjust the mask in the device tree to
reserve irq12 which is used by PS/2 mouse.Signed-off-by: Bin Meng
Reviewed-by: Simon Glass
24 Aug, 2015
1 commit
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Conflicts:
configs/socfpga_arria5_defconfig
configs/socfpga_cyclone5_defconfig
configs/socfpga_socrates_defconfigMerged these by hand and re-ran savedefconfig on them.
Signed-off-by: Tom Rini
23 Aug, 2015
8 commits
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Pull out the ArriaV SoCDK clock config from ancient Altera U-Boot
"rel_socfpga_v2013.01.01_15.05.01_pr" and implant those values into
mainline to get a booting ArriaV SoCDK.Signed-off-by: Marek Vasut
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Repair the maintainer entries so they match the current state of code.
Signed-off-by: Marek Vasut
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Now that we're actually converting the QTS-generated header files,
we can even adjust their data types. A good candidate for this is
the pinmux table, where each entry can have value in the range of
0..3, but each element is declared as unsigned long. By changing
the type to u8, we can save over 600 Bytes from the SPL, so do it.
This patch also constifies the array.Signed-off-by: Marek Vasut
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Signed-off-by: Marek Vasut
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Just remove the ArriaV specific parts from the CycloneV SoCDK board
and they are no longer needed now.Signed-off-by: Marek Vasut
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Just remove the CycloneV specific parts from the ArriaV SoCDK board
and they are no longer needed now.Signed-off-by: Marek Vasut
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The board/altera/socfpga directory is not a generic SoCFPGA machine
anymore, but instead it represents the Altera SoCDK board. To make
matters more complicated, it represents both CycloneV and ArriaV
variant.On the other hand, nowadays, the content of this board directory is
mostly comprised of QTS-generated header files, while all the generic
code is in arch/arm/mach-socfpga already.Thus, this patch splits the board/altera/socfpga into a separate
board directory for ArriaV SoCDK and CycloneV SoCDK, so that each
can be populated with the correct QTS-generated header files for
that particular board.Signed-off-by: Marek Vasut
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Move the wrappers for QTS-generated files into platform directory
out of the board directory. The trick here is to add -I to CFLAGS
such that it points to the board directory in source tree and thus
the qts/ directory there is still reachable.Signed-off-by: Marek Vasut
21 Aug, 2015
3 commits
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Since sama5d3xek boards has different type of dtb blobs, so we need to detect
the cpu type in runtime.So we add a new variable $dtb_name. if $dtb_name is not defined, we just use
at91-${board_name}.dtbas the $dtb_name. Otherwise, we will just load the dtb with
$dtb_name.For sama5d3xek, we will detect cpu type and make up $dtb_name in
runtime.Signed-off-by: Josh Wu
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Bootlog:
U-Boot SPL 2015.10-rc1-00452-g96a7ed1 (Aug 17 2015 - 10:32:21)
mci: setting clock 258000 Hz, block size 512
mci: setting clock 258000 Hz, block size 512
mci: setting clock 258000 Hz, block size 512
mci: setting clock 33024000 Hz, block size 512
reading u-boot.img
reading u-boot.imgU-Boot 2015.10-rc1-00452-g96a7ed1 (Aug 17 2015 - 10:32:21 +0000)
CPU: AT91SAM9G45
Crystal frequency: 12 MHz
CPU clock : 400 MHz
Master clock : 133.333 MHz
Watchdog enabled
DRAM: 256 MiB
WARNING: Caches not enabled
MMC: mci: 0
mci: setting clock 260416 Hz, block size 512
mci: setting clock 260416 Hz, block size 512
mci: setting clock 260416 Hz, block size 512
mci: setting clock 33333333 Hz, block size 512
reading uboot.env
In: serial
Out: serial
Err: serial
Net: macb0
Error: macb0 address not set.Hit any key to stop autoboot: 0
U-Boot>Signed-off-by: Erik van Luijk
[add 'picosam9g45_defconfig' to MAINTAINERS]
Signed-off-by: Andreas Bießmann -
To enable the clocks on the at91 boards a constant (0x4) is used.
This is replaced with a define in at91_pmc.h (1 << 2).Signed-off-by: Erik van Luijk
Reviewed-by: Andreas Bießmann
