08 Jan, 2014
1 commit
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The omap3_zoom2 board has not been updated for a correct CONFIG_SYS_HZ
and Tom Rix's email has long been bouncing.Signed-off-by: Tom Rini
06 Jan, 2014
1 commit
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Conflicts:
include/micrel.hThe conflict above was trivial, caused by four lines being
added in both branches with different whitepace.
03 Jan, 2014
1 commit
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Enable fuse supply before fuse programming and disable after.
Signed-off-by: Sergey Alyoshin
Reviewed-by: Benoît Thébaudeau
19 Dec, 2013
1 commit
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Create the i2c adapter object for the fifth bus on SoC with more than
4 buses. This allow using all the bus available on T30.Signed-off-by: Alban Bedel
Acked-by: Heiko Schocher
Signed-off-by: Tom Warren
11 Dec, 2013
2 commits
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Conflicts:
board/samsung/trats2/trats2.c
include/configs/exynos5250-dt.hSigned-off-by: Tom Rini
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Conflicts:
arch/arm/cpu/armv7/rmobile/Makefile
doc/README.scrapyardNeeded manual fix:
arch/arm/cpu/armv7/omap-common/Makefile
board/compulab/cm_t335/u-boot.lds
10 Dec, 2013
7 commits
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Signed-off-by: Soren Brinkmann
Signed-off-by: Michal Simek -
This adds a SPI flash driver which simulates SPI flash clients.
Currently supports the bare min that U-Boot requires: you can
probe, read, erase, and write. Should be easy to extend to make
it behave more exactly like a real SPI flash, but this is good
enough to merge now.sjg@chromium.org added a README and tidied up code a little.
Added a required map_sysmem() for sandbox.Signed-off-by: Mike Frysinger
Signed-off-by: Simon Glass -
This adds a SPI framework for people to hook up simulated SPI clients.
Signed-off-by: Mike Frysinger
Signed-off-by: Simon Glass -
This allows us to put the SPI flash chip inside the SPI interface node,
with U-Boot finding the correct bus and chip select automatically.Signed-off-by: Simon Glass
09 Dec, 2013
2 commits
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Signed-off-by: Andreas Bießmann
Acked-by: Jens Scharsig (BuS Elektronik)
Tested-by: Jens Scharsig (BuS Elektronik)
Acked-by: Scott Wood -
This patch define new names for GPIO pins on at91 devices. Follow up patches
will convert the whole infrastructure to use these new definitions.Signed-off-by: Andreas Bießmann
Tested-by: Bo Shen
08 Dec, 2013
4 commits
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Faraday FTSDC021 is a controller which is compliant with
SDHCI v3.0, SDIO v2.0 and MMC v4.3.However this driver is only verified with SD memory cards.
Signed-off-by: Kuo-Jung Su
Acked-by: Pantelis Antoniou
CC: Andy Fleming -
Existing eSDHC SPL framework assumes booting from sd-image
with boot_format header which contains final u-boot Image
offset and size. No such header is present in case of
corenet devices like T1040 as corenet deivces use PBI-RCW
based intialization.So, for corenet deives, SPL bootloader use values provided
at compilation time. These values can be defined in board
specific config file.Signed-off-by: Priyanka Jain
Acked-by: Pantelis Antoniou -
If platform provides "host->fifoth_val" it will be used for
initialization of DWMCI_FIFOTH register. Otherwise default value will be
used.This implementation allows:
* escape unclear and recursive calculations that are currently in use
* use whatever custom value for DWMCI_FIFOTH initialization if any
particular SoC requires itSigned-off-by: Alexey Brodkin
Cc: Mischa Jonker
Cc: Alim Akhtar
Cc: Rajeshwari Shinde
Cc: Jaehoon Chung
Cc: Amar
Cc: Kyungmin Park
Cc: Minkyu Kang
Cc: Simon Glass
Cc: Pantelis Antoniou
Cc: Andy Fleming
Acked-by: Jaehoon Chung
Acked-by: Pantelis Antoniou -
dw-mmc.c is the general driver file.
So, remove the exynos specific code at dw-mmc.c.
Instead, exynos specific cod can be move into exynos-dw_mmc.c.Signed-off-by: Jaehoon Chung
Acked-by: Alexey Brodkin
Acked-by: Pantelis Antoniou
Acked-by: Minkyu Kang
06 Dec, 2013
6 commits
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In commit bb1f327 we removed the UHH reset to fix NFS root (over usb
ethernet) problems with Beagleboard (3530 ES1.0). However, this
seems to cause USB detection problems for Pandaboard, about (3/8).On further investigation, it seems that doing the UHH reset is not
the cause of the original Beagleboard problem, but in the way the reset
was done.This patch adds proper UHH RESET mechanism for OMAP3 and OMAP4/5 based
on the UHH_REVISION register. This should fix the Beagleboard NFS
problem as well as the Pandaboard USB detection problem.Reported-by: Tomi Valkeinen
CC: Stefan Roese
Reviewed-by: Stefan Roese
Signed-off-by: Roger Quadros -
For invalid bus number, current code returns NULL in the default case of
switch-case statements. In additional, pins[bus] is always not NULL because
it is the address of specific row of the two-dimensional array.
Thus this patch removes these unnecessary test.Signed-off-by: Axel Lin
Acked-by: Scott Jiang
Signed-off-by: Sonic Zhang -
For invalid bus number, current code returns NULL in the default case of
switch-case statements. In additional, pins[bus] is always not NULL because
it is the address of specific row of the two-dimensional array.
Thus this patch removes these unnecessary test.Signed-off-by: Axel Lin
Acked-by: Scott Jiang
Signed-off-by: Sonic Zhang -
This patch adds the U_BOOT_I2C_ADAP_COMPLETE defines for channels
on Exynos5420 and Exynos5250 and also adds support for init function
for hsi2c channelsSigned-off-by: Naveen Krishna Chatradhi
05 Dec, 2013
8 commits
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Writing zero into I2Ci.I2C_CNT register causes random I2C failures in OMAP3
based devices. This seems to be related to the following advisory which
apears in multiple erratas for OMAP3 SoCs (OMAP35xx, DM37xx), as well as
OMAP4430 TRM:Advisory:
I2C Module Does Not Allow 0-Byte Data Requests
Details:
When configured as the master, the I2C module does not allow 0-byte data
transfers. Note: Programming I2Ci.I2C_CNT[15:0]: DCOUNT = 0 will cause
undefined behavior.
Workaround(s):
No workaround. Do not use 0-byte data requests.The writes in question are unnecessary from a functional point of view.
Most of them are done after I/O has finished, and the only one that preceds
I/O (in i2c_probe()) is also unnecessary because a stop bit is sent before
actual data transmission takes place.Therefore, remove all writes that zero the cnt register.
Cc: Heiko Schocher
Cc: Thomas Petazzoni
Cc: Tom Rini
Cc: Lubomir Popov
Cc: Enric Balletbo Serra
Signed-off-by: Nikita Kiryanov
Tested-by: Thomas Petazzoni
Tested-by: Lubomir Popov -
For a eeprom with a 2-bytes address (e.g., Ateml AT24C1024B),
the r/w address should be serial out in MSB order.Signed-off-by: Kuo-Jung Su
Cc: Heiko Schocher -
Replace the legacy i2c model with the new one.
Signed-off-by: Kuo-Jung Su
Cc: Heiko Schocher -
Coding style cleanup
Signed-off-by: Kuo-Jung Su
Cc: Heiko Schocher -
Fix clock value initialisation for Exynos other than Exynos5 for hsi2c.
Signed-off-by: Piotr Wilczek
Signed-off-by: Kyungmin Park
Cc: Minkyu Kang
Cc: Heiko Schocher -
This patch adapts the s3c24x0 driver to the new i2c framework.
Config file is modified for all the boards that use the driver.Signed-off-by: Piotr Wilczek
Signed-off-by: Kyungmin Park
CC: Minkyu Kang
CC: Heiko Schocher
CC: Inderpal Singh
CC: David Müller
CC: Chander Kashyap
CC: Lukasz Majewski
Tested-by: Naveen Krishna Chatradhi
Reviewed-by: Naveen Krishna Chatradhi -
Existing eSPI SPL framework assumes booting from spi-image
with boot_format header which contains final u-boot Image
offset and size. No such header is present in case of
corenet devices like T1040 as corenet deivces use PBI-RCW
based intialization.So, for corenet deives, SPL bootloader use values provided
at compilation time. These values can be defined in board
specific config file.Signed-off-by: Priyanka Jain
Acked-by: York Sun -
In 48ec5291, only TX path was optimized; this does the same also for RX
path. This results in huge increase of TFTP throughput on custom am3352
board (from 312KiB/s to 1.8MiB/s) and eliminates occasional transfer
timeouts.Signed-off-by: Vladimir Koutny
Cc: Mugunthan V N
Cc: Joe Hershberger
Cc: Tom Rini
04 Dec, 2013
4 commits
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Align the ATA ID buffer to the cache-line boundary. This gets rid
of the below error mesages on ARM v7 platforms.scanning bus for devices...
ERROR: v7_dcache_inval_range - start address is not aligned - 0xfee48618
ERROR: v7_dcache_inval_range - stop address is not aligned - 0xfee48818CC: Aneesh V
Signed-off-by: Roger Quadros -
If malloc() fails, we don't want to continue in ahci_init() and
ahci_init_one(). Also print a more informative error message on
malloc() failures.CC: Rob Herring
Signed-off-by: Roger Quadros -
Added chip type detection and twl6032
support in the battery control
and charge functions.Based on Balaji T K patches for TI u-boot.
Signed-off-by: Oleg Kosheliev
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The data struct is used to support different
PMIC chip types. It contains the chip type and
the data (e.g. registers addresses, adc multiplier)
which is different for twl6030 and twl6032.
Replaced some hardcoded values with the
structure vars.Based on Balaji T K patches for TI u-boot.
Signed-off-by: Oleg Kosheliev
02 Dec, 2013
3 commits
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Signed-off-by: Soren Brinkmann
Signed-off-by: Michal Simek
Series-to: trini, uboot