06 Feb, 2014
1 commit
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When ARCH_DMA_MINALIGN is greater than header size of the bit file, and buf is
not aligned, new_buf address became greater then buf_start address and the
load_word loop corrupts bit file data.A work around is to decrease new_buf of ARCH_DMA_MINALIGN, it might corrupt data
before buf but permits to load correctly.Signed-off-by: Stany MARCEL
Signed-off-by: Michal Simek
18 Nov, 2013
1 commit
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- Descend into drivers/fpga/ only when CONFIG_FPGA=y
- Descend into drivers/bios_emulator only when CONFIG_BIOSEMU=ySigned-off-by: Masahiro Yamada
06 Nov, 2013
2 commits
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DMA doesn't work when src is placed below 1MB limit.
Signed-off-by: Michal Simek
Acked-by: Jagannadha Sutradharudu Teki -
Buffers must be cache and dma aligned.
Signed-off-by: Jagannadha Sutradharudu Teki
Signed-off-by: Michal Simek
01 Nov, 2013
1 commit
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Signed-off-by: Masahiro Yamada
15 Oct, 2013
1 commit
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Signed-off-by: Wolfgang Denk
12 Aug, 2013
2 commits
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Some versions of the Zynq first stage boot loader enable PCAP loopback
during boot regardless of whether or not the boot image includes PL
configuration. This behavior only appears in certain boot modes (notably
QSPI boot). Attempting to configure the PL with the loopback bit set
will result in timeouts and will prevent successful configuration.In order to avoid this problem, and to avoid dependency on the version
of the FSBL used to boot the system, ensure that the loopback enable bit
is cleared when loading the driver.Signed-off-by: Soren Brinkmann
Signed-off-by: Michal Simek -
- Add support for zc7100 device.
- FPGA programming on few of the SOC(zc7100) takes more
than 1sec, hence increased the program time by 4sec to
sync' all soc's.Signed-off-by: Jagannadha Sutradharudu Teki
Signed-off-by: Michal Simek
24 Jul, 2013
1 commit
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Signed-off-by: Wolfgang Denk
[trini: Fixup common/cmd_io.c]
Signed-off-by: Tom Rini
06 May, 2013
6 commits
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Ensure that wrong bitstream won't be loaded
to current device.Signed-off-by: Michal Simek
Reviewed-by: Tom Rini -
Devcfg device requires to load bitstream in binary format.
But u-boot also has an option for loading bitstream in bit
format. Let's handle both cases by zynqpl driver.
Also add suport for loading partial bitstreams.The first driver version was done by:
Joe HershbergerSigned-off-by: Michal Simek
Reviewed-by: Tom Rini -
All fpga functions use devnum as int. Only fpga_loadbitstream
is using it as unsinged long dev.
This patch synchronize it.Signed-off-by: Michal Simek
Reviewed-by: Tom Rini -
In bitstream decoding you can directly check device
which you want to load and in fpga.c are fpga_validate
and fpga_dev_info functions which should be used for it.Signed-off-by: Michal Simek
Reviewed-by: Tom Rini -
CONFIG_FPGA in past was a bitfield where bits
were use for vendor identification.This fix should be the part of this commit:
"Improve configuration of FPGA subsystem"
(sha1: 0133502e39ff89b67c26cb4015e0e7e8d9571184)Signed-off-by: Michal Simek
Reviewed-by: Tom Rini -
No functional changes.
Signed-off-by: Michal Simek
Reviewed-by: Tom Rini
02 Apr, 2013
1 commit
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'bool' is defined in random places. This patch consolidates them into a
single header file include/linux/types.h, using stdbool.h introduced in C99.All other #define, typedef and enum are removed. They are all consistent with
true = 1, false = 0.Replace FALSE, False with false. Replace TRUE, True with true.
Skip *.py, *.php, lib/* files.Signed-off-by: York Sun
30 Oct, 2012
1 commit
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Deassert the CONFIG pin before asserting it again. This assures that the
FPGA will be resetted and therefore configuration will be correctly
enabled.This is also already done on other FPGA's, e.g. Stratix.
Signed-off-by: Stephan Gatzka
Signed-off-by: Stefan Roese
05 Mar, 2012
1 commit
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Signed-off-by: Thomas Weber
05 Jan, 2012
1 commit
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CONFIG_SYS_FPGA_PROG_FEEDBACK was already introduced to print
the current status of FPGA loading - an undef in the code made this
CONFIG_ useless.Signed-off-by: Stefano Babic
17 Nov, 2011
1 commit
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Fix:
ivm_core.c: In function 'ispVMLCOUNT':
ivm_core.c:2105:16: warning: unused variable 'usByte'Signed-off-by: Stefano Babic
CC: Wolfgang Denk
28 Oct, 2011
1 commit
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lattice.c:319:4: warning: format '%x' expects type 'unsigned int', but argument
3 has type 'const char *'
lattice.c:319:4: warning: format '%x' expects type 'unsigned int', but argument
4 has type 'long unsigned int'Signed-off-by: Marek Vasut
Cc: Wolfgang Denk
Cc: Simon Glass
Cc: Mike Frysinger
05 Sep, 2011
1 commit
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The Lattice code was missed by commit e6a857d "fpga: constify to fix
build warning" resulting in such warnings:fpga.c: In function 'fpga_load':
fpga.c:238: warning: passing argument 2 of 'lattice_load' discards qualifiers from pointer target type
fpga.c: In function 'fpga_dump':
fpga.c:278: warning: passing argument 2 of 'lattice_dump' discards qualifiers from pointer target typeSigned-off-by: Wolfgang Denk
cc: Stefano Babic
01 Aug, 2011
1 commit
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Fix compiler warning:
cmd_fpga.c:318: warning: passing argument 3 of 'fit_image_get_data'
from incompatible pointer typeAdding the needed 'const' here entails a whole bunch of additonal
changes all over the FPGA code.Signed-off-by: Wolfgang Denk
Cc: Andre Schwarz
Cc: Murray Jensen
Acked-by: Andre Schwarz
28 Jul, 2011
2 commits
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Support FPGAs which use Fast Passive Parallel configuration
Signed-off-by: Michael Jones
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Signed-off-by: Michael Jones
Acked-by: Detlev Zundel
01 Dec, 2010
1 commit
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Currently the hardware was left in an undefined state in case Spartan3
serial load failed. This patch adds Xilinx_abort_fn to give the board
a possibility to clean up in this case.Signed-off-by: Wolfgang Wegner
18 Nov, 2010
1 commit
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Before this commit, weak symbols were not overridden by non-weak symbols
found in archive libraries when linking with recent versions of
binutils. As stated in the System V ABI, "the link editor does not
extract archive members to resolve undefined weak symbols".This commit changes all Makefiles to use partial linking (ld -r) instead
of creating library archives, which forces all symbols to participate in
linking, allowing non-weak symbols to override weak symbols as intended.
This approach is also used by Linux, from which the gmake function
cmd_link_o_target (defined in config.mk and used in all Makefiles) is
inspired.The name of each former library archive is preserved except for
extensions which change from ".a" to ".o". This commit updates
references accordingly where needed, in particular in some linker
scripts.This commit reveals board configurations that exclude some features but
include source files that depend these disabled features in the build,
resulting in undefined symbols. Known such cases include:
- disabling CMD_NET but not CMD_NFS;
- enabling CONFIG_OF_LIBFDT but not CONFIG_QE.Signed-off-by: Sebastien Carlier
28 Oct, 2010
1 commit
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Signed-off-by: Wolfgang Denk
19 Oct, 2010
1 commit
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Commit 3b8ac464 "FPGA: add support for downloading Lattice bitstream"
added support for Lattice devices, but failed to add #ifdef's that are
needed when building for non-Lattice devices, which results in build
failures like these:Configuring for GEN860T board...
drivers/fpga/libfpga.a(fpga.o): In function `fpga_dev_info':
/home/wd/git/u-boot/work/drivers/fpga/fpga.c:145: undefined reference to `lattice_info'
drivers/fpga/libfpga.a(fpga.o): In function `fpga_dump':
/home/wd/git/u-boot/work/drivers/fpga/fpga.c:269: undefined reference to `lattice_dump'
drivers/fpga/libfpga.a(fpga.o): In function `fpga_load':
/home/wd/git/u-boot/work/drivers/fpga/fpga.c:233: undefined reference to `lattice_load'
make: *** [u-boot] Error 1Add the missing code.
Signed-off-by: Wolfgang Denk
Cc: Stefano Babic
14 Oct, 2010
1 commit
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The patch adds support to load a Lattice's bitstream
image (called VME file) into a Lattice FPGA. The code
containing the state machine delivered as part of
Lattice's ispVMtools is integrated.The FPGA is programmed using the JTAG interface. The
board maintainer must provide accessors to drive the
JTAG signals TCK, TMS, TDI and to get the value of the
input signal TDO.Signed-off-by: Stefano Babic
25 Mar, 2010
1 commit
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Using seperate function calls for each bit-bang of slave serial
load can be painfully slow. This patch adds the possibility to
supply a block write function that loads the complete block of
data in one call (like it can already be done with Altera FPGAs).
On an MCF5373L (240 MHz) loading an XC3S4000 this reduces the load
time from around 15 seconds to around 3 secondsSigned-off-by: Wolfgang Wegner
03 Oct, 2009
1 commit
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PPC boards are the only users of the current FPGA code which is littered
with manual relocation fixups. Now that proper relocation is supported
for PPC boards, remove FPGA manual relocation.Signed-off-by: Peter Tyser
22 Feb, 2009
2 commits
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This patch does some minor fixing of the Xilinx Spartan III
FPGA boot code:- Fixed call order of post configuration callback and
success message printing (result of copy-paste?)
- remove obsolete comment
- minor coding style cleanupSigned-off-by: Matthias Fuchs
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This patch does some minor fixing of the Xilinx Spartan II
FPGA boot code:- Fixed call order of post configuration callback and
success message printing (result of copy-paste?)
- relocate post configuration callback only when it
is implemented
- remove obsolete comment
- minor coding style cleanupSigned-off-by: Matthias Fuchs
06 Dec, 2008
1 commit
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Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD