06 Feb, 2014

1 commit

  • When ARCH_DMA_MINALIGN is greater than header size of the bit file, and buf is
    not aligned, new_buf address became greater then buf_start address and the
    load_word loop corrupts bit file data.

    A work around is to decrease new_buf of ARCH_DMA_MINALIGN, it might corrupt data
    before buf but permits to load correctly.

    Signed-off-by: Stany MARCEL
    Signed-off-by: Michal Simek

    Novasys Ingenierie
     

18 Nov, 2013

1 commit


06 Nov, 2013

2 commits


01 Nov, 2013

1 commit


15 Oct, 2013

1 commit


12 Aug, 2013

2 commits

  • Some versions of the Zynq first stage boot loader enable PCAP loopback
    during boot regardless of whether or not the boot image includes PL
    configuration. This behavior only appears in certain boot modes (notably
    QSPI boot). Attempting to configure the PL with the loopback bit set
    will result in timeouts and will prevent successful configuration.

    In order to avoid this problem, and to avoid dependency on the version
    of the FSBL used to boot the system, ensure that the loopback enable bit
    is cleared when loading the driver.

    Signed-off-by: Soren Brinkmann
    Signed-off-by: Michal Simek

    Soren Brinkmann
     
  • - Add support for zc7100 device.
    - FPGA programming on few of the SOC(zc7100) takes more
    than 1sec, hence increased the program time by 4sec to
    sync' all soc's.

    Signed-off-by: Jagannadha Sutradharudu Teki
    Signed-off-by: Michal Simek

    Michal Simek
     

24 Jul, 2013

1 commit


06 May, 2013

6 commits


02 Apr, 2013

1 commit

  • 'bool' is defined in random places. This patch consolidates them into a
    single header file include/linux/types.h, using stdbool.h introduced in C99.

    All other #define, typedef and enum are removed. They are all consistent with
    true = 1, false = 0.

    Replace FALSE, False with false. Replace TRUE, True with true.
    Skip *.py, *.php, lib/* files.

    Signed-off-by: York Sun

    York Sun
     

30 Oct, 2012

1 commit


05 Mar, 2012

1 commit


05 Jan, 2012

1 commit


17 Nov, 2011

1 commit


28 Oct, 2011

1 commit

  • lattice.c:319:4: warning: format '%x' expects type 'unsigned int', but argument
    3 has type 'const char *'
    lattice.c:319:4: warning: format '%x' expects type 'unsigned int', but argument
    4 has type 'long unsigned int'

    Signed-off-by: Marek Vasut
    Cc: Wolfgang Denk
    Cc: Simon Glass
    Cc: Mike Frysinger

    Marek Vasut
     

05 Sep, 2011

1 commit

  • The Lattice code was missed by commit e6a857d "fpga: constify to fix
    build warning" resulting in such warnings:

    fpga.c: In function 'fpga_load':
    fpga.c:238: warning: passing argument 2 of 'lattice_load' discards qualifiers from pointer target type
    fpga.c: In function 'fpga_dump':
    fpga.c:278: warning: passing argument 2 of 'lattice_dump' discards qualifiers from pointer target type

    Signed-off-by: Wolfgang Denk
    cc: Stefano Babic

    Wolfgang Denk
     

01 Aug, 2011

1 commit

  • Fix compiler warning:

    cmd_fpga.c:318: warning: passing argument 3 of 'fit_image_get_data'
    from incompatible pointer type

    Adding the needed 'const' here entails a whole bunch of additonal
    changes all over the FPGA code.

    Signed-off-by: Wolfgang Denk
    Cc: Andre Schwarz
    Cc: Murray Jensen
    Acked-by: Andre Schwarz

    Wolfgang Denk
     

28 Jul, 2011

2 commits


01 Dec, 2010

1 commit


18 Nov, 2010

1 commit

  • Before this commit, weak symbols were not overridden by non-weak symbols
    found in archive libraries when linking with recent versions of
    binutils. As stated in the System V ABI, "the link editor does not
    extract archive members to resolve undefined weak symbols".

    This commit changes all Makefiles to use partial linking (ld -r) instead
    of creating library archives, which forces all symbols to participate in
    linking, allowing non-weak symbols to override weak symbols as intended.
    This approach is also used by Linux, from which the gmake function
    cmd_link_o_target (defined in config.mk and used in all Makefiles) is
    inspired.

    The name of each former library archive is preserved except for
    extensions which change from ".a" to ".o". This commit updates
    references accordingly where needed, in particular in some linker
    scripts.

    This commit reveals board configurations that exclude some features but
    include source files that depend these disabled features in the build,
    resulting in undefined symbols. Known such cases include:
    - disabling CMD_NET but not CMD_NFS;
    - enabling CONFIG_OF_LIBFDT but not CONFIG_QE.

    Signed-off-by: Sebastien Carlier

    Sebastien Carlier
     

28 Oct, 2010

1 commit


19 Oct, 2010

1 commit

  • Commit 3b8ac464 "FPGA: add support for downloading Lattice bitstream"
    added support for Lattice devices, but failed to add #ifdef's that are
    needed when building for non-Lattice devices, which results in build
    failures like these:

    Configuring for GEN860T board...
    drivers/fpga/libfpga.a(fpga.o): In function `fpga_dev_info':
    /home/wd/git/u-boot/work/drivers/fpga/fpga.c:145: undefined reference to `lattice_info'
    drivers/fpga/libfpga.a(fpga.o): In function `fpga_dump':
    /home/wd/git/u-boot/work/drivers/fpga/fpga.c:269: undefined reference to `lattice_dump'
    drivers/fpga/libfpga.a(fpga.o): In function `fpga_load':
    /home/wd/git/u-boot/work/drivers/fpga/fpga.c:233: undefined reference to `lattice_load'
    make: *** [u-boot] Error 1

    Add the missing code.

    Signed-off-by: Wolfgang Denk
    Cc: Stefano Babic

    Wolfgang Denk
     

14 Oct, 2010

1 commit

  • The patch adds support to load a Lattice's bitstream
    image (called VME file) into a Lattice FPGA. The code
    containing the state machine delivered as part of
    Lattice's ispVMtools is integrated.

    The FPGA is programmed using the JTAG interface. The
    board maintainer must provide accessors to drive the
    JTAG signals TCK, TMS, TDI and to get the value of the
    input signal TDO.

    Signed-off-by: Stefano Babic

    Stefano Babic
     

25 Mar, 2010

1 commit

  • Using seperate function calls for each bit-bang of slave serial
    load can be painfully slow. This patch adds the possibility to
    supply a block write function that loads the complete block of
    data in one call (like it can already be done with Altera FPGAs).
    On an MCF5373L (240 MHz) loading an XC3S4000 this reduces the load
    time from around 15 seconds to around 3 seconds

    Signed-off-by: Wolfgang Wegner

    Wolfgang Wegner
     

03 Oct, 2009

1 commit

  • PPC boards are the only users of the current FPGA code which is littered
    with manual relocation fixups. Now that proper relocation is supported
    for PPC boards, remove FPGA manual relocation.

    Signed-off-by: Peter Tyser

    Peter Tyser
     

22 Feb, 2009

2 commits

  • This patch does some minor fixing of the Xilinx Spartan III
    FPGA boot code:

    - Fixed call order of post configuration callback and
    success message printing (result of copy-paste?)
    - remove obsolete comment
    - minor coding style cleanup

    Signed-off-by: Matthias Fuchs

    Matthias Fuchs
     
  • This patch does some minor fixing of the Xilinx Spartan II
    FPGA boot code:

    - Fixed call order of post configuration callback and
    success message printing (result of copy-paste?)
    - relocate post configuration callback only when it
    is implemented
    - remove obsolete comment
    - minor coding style cleanup

    Signed-off-by: Matthias Fuchs

    Matthias Fuchs
     

06 Dec, 2008

1 commit