11 Dec, 2018
1 commit
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Add TFA boot flow for some Layerscape platforms
Add support for lx2160a SoC[trini: Add a bunch of missing MAINTAINERS entries]
Signed-off-by: Tom Rini
07 Dec, 2018
1 commit
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TFABOOT support includes:
- ls1012ardb_tfa_defconfig to be loaded by trusted firmware
- environment address and size changes for TFABOOT
- define BOOTCOMMAND for TFABOOT
- enable PFE validation for secure bootSigned-off-by: Rajesh Bhagat
Signed-off-by: Vinitha V Pillai
Signed-off-by: Pankit Garg
Reviewed-by: York Sun
08 Aug, 2018
1 commit
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Add command "boot_bank X" to switch the boot bank to either 1 or 2.
Signed-off-by: Jagdish Gediya
Reviewed-by: York Sun
09 Jun, 2018
1 commit
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PPA firmware and header address may vary depending upon different
boards, configure ppa firmware and header address in board specific
Kconfig.Signed-off-by: Vinitha V Pillai
Signed-off-by: Jagdish Gediya
Signed-off-by: Bhaskar Upadhaya
Reviewed-by: York Sun
07 May, 2018
1 commit
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When U-Boot started using SPDX tags we were among the early adopters and
there weren't a lot of other examples to borrow from. So we picked the
area of the file that usually had a full license text and replaced it
with an appropriate SPDX-License-Identifier: entry. Since then, the
Linux Kernel has adopted SPDX tags and they place it as the very first
line in a file (except where shebangs are used, then it's second line)
and with slightly different comment styles than us.In part due to community overlap, in part due to better tag visibility
and in part for other minor reasons, switch over to that style.This commit changes all instances where we have a single declared
license in the tag as both the before and after are identical in tag
contents. There's also a few places where I found we did not have a tag
and have introduced one.Signed-off-by: Tom Rini
23 Mar, 2018
2 commits
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This patch enables ethernet support for ls1012a2g5rdb.
Signed-off-by: Calvin Johnson
Signed-off-by: Bhaskar Upadhaya
Acked-by: Joe Hershberger -
This patch enables ethernet support for ls1012ardb.
Signed-off-by: Calvin Johnson
Signed-off-by: Anjaneyulu Jagarlmudi
Acked-by: Joe Hershberger
16 Jan, 2018
1 commit
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LS1012A-2G5RDB belongs to LS1012A family with features 2 2.5G SGMII
PFE MAC, SATA, USB 2.0/3.0, WiFi DDR, eMMC, QuadSPI, UART.Signed-off-by: Bhaskar Upadhaya
Reviewed-by: York Sun
15 Dec, 2017
3 commits
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I2C reading for DIP switch setting is not reliable for LS1012ARDB
RevD and later versions. This patch is to add hwconfig support to
enable/disable eSDHC1 manually for these boards. Also drop 'status'
fix-up for eSDHC0 and leave it as it is. It shouldn't always be
fixed up with 'okay'.Signed-off-by: Yangbo Lu
Reviewed-by: York Sun -
Add LS1012ARDB RevC/RevC1/RevC2/RevD/RevE information and
detect it when u-boot starts up.Signed-off-by: Yangbo Lu
Reviewed-by: York Sun -
This patch is to clean up definitions for I2C IO expanders.
The value 0x10 of __SW_BOOT_EMU is wrong. It should be 0x2.
Fixed it in this patch.Signed-off-by: Yangbo Lu
Reviewed-by: York Sun
11 Sep, 2017
1 commit
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CoreLink Cache Coherent Interconnect (CCI) provides full cache
coherency between two clusters of multi-core CPUs and I/O coherency
for devices and I/O masters.This patch add new config option SYS_FSL_HAS_CCI400 and moves
existing register space definaton of CCI-400 bus to fsl_immap to be
shared. CONFIG_SYS_CCI400_ADDR is replaced with SYS_CCI400_OFFSET
in Kconfig.Signed-off-by: Ashish Kumar
Signed-off-by: Prabhakar Kushwaha
[YS: revised commit message, squashed patches for armv8 and armv7]
Reviewed-by: York Sun
18 Apr, 2017
1 commit
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Add QSPI Secure Boot target to enable chain of trust
Signed-off-by: Sumit Garg
Signed-off-by: Vinitha Pillai
Reviewed-by: Ruchika Gupta
Reviewed-by: York Sun
14 Mar, 2017
2 commits
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In early MMU table, DDR has to be mapped as device memory to avoid
speculative access. After DDR is initialized, it needs to be updated
to normal memory to allow code execution. To simplify the code,
dram_init() is moved into a common file as a weak function.Signed-off-by: York Sun
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For ARMv8 Layerscape SoCs, secure memory and MC memorey are reserved
at the end of DDR. DDR is spit into two or three banks. This patch
reverts commit aabd7ddb and simplifies the calculation of reserved
memory, and moves the code into common SoC file. Secure memory is
carved out first. DDR bank size is reduced. Reserved memory is then
allocated on the top of available memory. U-Boot still has access
to reserved memory as data transferring is needed. Device tree is
fixed with reduced memory size to hide the reserved memory from OS.
The same region is reserved for efi_loader.Signed-off-by: York Sun
04 Feb, 2017
2 commits
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The PPA implements PSCI which requires for power managment.
Added support of PPA for LS1012AQDS, LS1012ARDB and LS1012AFRDM.
Signed-off-by: Hou Zhiqiang
Signed-off-by: Abhimanyu Saini
Signed-off-by: Prabhakar Kushwaha
Reviewed-by: York Sun -
PPA binary needs to be relocated on secure DDR, hence marking out
a portion of DDR as secure if CONFIG_SYS_MEM_RESERVE_SECURE flag
is setSigned-off-by: Hou Zhiqiang
Signed-off-by: Abhimanyu Saini
Signed-off-by: Prabhakar Kushwaha
Reviewed-by: York Sun
24 Jan, 2017
1 commit
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Introduce board/freescale/common/Kconfig so that we have a single place
for CONFIG options that are shared between ARM and PowerPC NXP platforms.Cc: York Sun
Signed-off-by: Tom Rini
Reviewed-by: York Sun
19 Jan, 2017
1 commit
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On LS1012ARDB board, three dual 1:4 mux/demux devices drive the SDHC2
signals to eMMC, SDIO wifi, SPI and Ardiuno shield. Only when we select
eMMC and SDIO wifi, the SDHC2 could be used. Otherwise, the command
inhibit bits of eSDHC2_PRSSTAT register will never release. This would
cause below continious error messages in linux since it uses polling
mode to detect card.
"mmc1: Controller never released inhibit bit(s)."
"mmc1: Controller never released inhibit bit(s)."
"mmc1: Controller never released inhibit bit(s)."
This patch is to define esdhc_status_fixup function for RDB to disable
SDHC2 status if no SDIO wifi or eMMC is selected.Signed-off-by: Yangbo Lu
Reviewed-by: York Sun
26 Sep, 2016
1 commit
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Instead of using multiple macros, a data structure is used to pass
board-specific parameters to MMDC DDR driver.Signed-off-by: York Sun
CC: Shengzhou Liu
Reviewed-by: Tom Rini
15 Sep, 2016
3 commits
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This general MMDC driver adds basic support for Freescale MMDC
(Multi Mode DDR Controller). Currently MMDC is integrated on ARMv8
LS1012A SoC for DDR3L, there will be a update to this driver to
support more flexible configuration if new features (DDR4, multiple
controllers/chip selections, etc) are implimented in future.Meantime, reuse common MMDC driver for LS1012ARDB/LS1012AQDS/
LS1012AFRDM.Signed-off-by: Shengzhou Liu
Reviewed-by: York Sun -
As the access to serders protocol unselected PCIe controller will
hang. So disable the R/W permission to unselected PCIe controller
including its CCSR, IO space and memory space according to the
serders protocol field of RCW.Signed-off-by: Hou Zhiqiang
Reviewed-by: York Sun -
Move forward the basic non-secure access enable operation, so the
subsequent individual device access permission can override it.
And collect the dispersed callers in board level, and then move
them to SoC level.Signed-off-by: Hou Zhiqiang
Reviewed-by: York Sun
04 Jun, 2016
1 commit
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QorIQ LS1012A Reference Design System (LS1012ARDB) is a high-performance
development platform, with a complete debugging environment.
The LS1012ARDB board supports the QorIQ LS1012A processor and is
optimized to support the high-bandwidth DDR3L memory and
a full complement of high-speed SerDes ports.Signed-off-by: Calvin Johnson
Signed-off-by: Pratiyush Mohan Srivastava
Signed-off-by: Prabhakar Kushwaha
Reviewed-by: York Sun