13 Jan, 2014
2 commits
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Unified the bar code from read_ops into a spi_flash_bar()
Signed-off-by: Jagannadha Sutradharudu Teki
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- comment typo's
- func args have a proper namesSigned-off-by: Jagannadha Sutradharudu Teki
11 Jan, 2014
13 commits
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QEB code comprises of couple of flash register read/write operations,
this patch moved flash register operations on to sf_opSigned-off-by: Jagannadha Sutradharudu Teki
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Added macronix flash quad read/write commands support and
it's up to the respective controller driver usecase to
configure the respective commands by defining SPI RX/TX
operation modes from include/spi.h on the driver.Signed-off-by: Jagannadha Sutradharudu Teki
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This patch adds set QEB support for macronix flash devices
which are trying to program/read quad operations.Signed-off-by: Jagannadha Sutradharudu Teki
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Discovered the read dummy_byte based on the
configured read command.Signed-off-by: Jagannadha Sutradharudu Teki
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This patch adds support QUAD_IO_FAST read command.
Signed-off-by: Jagannadha Sutradharudu Teki
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Moved the flash params table from sf_probe.c and
placed on to sf_params.c, hence flash params file will
alter based on new addons.Signed-off-by: Jagannadha Sutradharudu Teki
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This patch enabled RD_FULL and WR_QPP for supported flashes
in micron, winbond and spansion.Remaining parts will be add in future patches.
Signed-off-by: Jagannadha Sutradharudu Teki
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This patch provides support to set the quad enable bit on flash.
quad enable bit needs to set before performing any quad IO
operations on respective SPI flashes.Currently added set quad enable bit for winbond and spansion flash
devices. stmicro flash doesn't require to set as qeb is volatile.
remaining flash devices support will add in future patches.Signed-off-by: Jagannadha Sutradharudu Teki
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This patch provides support to program a flash config register.
Configuration register contains the control bits used to configure
the different configurations and security features of a device.Signed-off-by: Jagannadha Sutradharudu Teki
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This patch add quad commands support like
- QUAD_PAGE_PROGRAM => for write program
- QUAD_OUTPUT_FAST ->> for read programSigned-off-by: Jagannadha Sutradharudu Teki
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Current sf uses FAST_READ command, this patch adds support to
use the different/extended read command.This implementation will determine the fastest command by taking
the supported commands from the flash and the controller, controller
is always been a priority.Signed-off-by: Jagannadha Sutradharudu Teki
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We have a sh_spi_clear_bit() function, there's no reason not to use it.
Signed-off-by: Axel Lin
Acked-by: Nobuhiro Iwamatsu
Reviewed-by: Jagannadha Sutradharudu Teki -
The Faraday FTSSP010 is a multi-function controller
which supports I2S/SPI/SSP/AC97/SPDIF. However This
patch implements only the SPI mode.NOTE:
The DMA and CS/Clock control logic has been altered
since hardware revision 1.19.0. So this patch
would first detects the revision id of the underlying
chip, and then switch to the corresponding software
control routines.Signed-off-by: Kuo-Jung Su
Signed-off-by: Jagannadha Sutradharudu Teki
CC: Tom Rini
10 Jan, 2014
2 commits
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Bringing in the MMC tree means that CONFIG_BOUNCE_BUFFER needed to be
added to include/configs/exynos5-dt.h now.Conflicts:
include/configs/exynos5250-dt.hSigned-off-by: Tom Rini
09 Jan, 2014
8 commits
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To add the DesignWare MMC driver support for Altera SOCFPGA. It
required information such as clocks and bus width from platform
specific files (SOCFPGA handoff files)Signed-off-by: Chin Liang See
Cc: Rajeshwari Shinde
Cc: Jaehoon Chung
Cc: Pantelis Antoniou
Cc: Wolfgang Denk
Acked-by: Pantelis Antoniou -
The eMMC and the SD-Card specifications describe the optional SET_DSR command.
During measurements at our lab we found that some cards implementing this feature
having really strong driver strengts per default. This can lead to voltage peaks
above the specification of the host on signal edges for data sent from a card to
the host.Since availability of a given card type may be shorter than the time a certain
hardware will be produced it is useful to have support for this command (Alternative
would be changing termination resistors and adapting the driver strength of the
host to the used card.)Following proposal for an implementation:
- new field that reflects CSD field DSR_IMP in struct mmc
- new field for design specific DSR value in struct mmc
- board code can set DSR value in mmc struct just after registering an controller
- mmc_startup sends the the stored DSR value before selecting a card, if DSR_IMP is setAdditionally the mmc command is extended to make is possible to play around with different
DSR values.The concept was tested on a i.MX53 based platform using a Micron eMMC card where the default
DSR is 0x0400 (12mA) but in our design 0x0100 (0x0100) were enough. To use this feature for
instance on a mx53loco one have to add a call to mmc_set_dsr() in board_mmc_init() after
calling fsl_esdhc_initialize() for the eMMC.Signed-off-by: Markus Niebel
Acked-by: Pantelis Antoniou -
Fixup prints to show where the print is done from, and
a few minor formatting/grammar issues.Signed-off-by: Darwin Rambo
Acked-by: Pantelis Antoniou -
Bounce buffer implementation takes care of proper data buffer alignemt
and correct flush/invalidation of data cache at once so we no longer
depend on input data variety and make sure CPU and MMC controller deal
with expected data in case of enabled data cache.Bounce buffer requires to add its definition (CONFIG_BOUNCE_BUFFER) in
board configuration, otherwise corresponding library won't be compiled
and linker will fail to build resulting executable.Difference since v1 - fixed compile-time warning with type casting to
"void *":Slight edit to remove UTF8 characters in the commit message.
Acked-by: Jaehoon Chung
Tested-by: Jaehoon Chung
Acked-by: Pantelis Antoniou====
passing argument 2 of 'bounce_buffer_start' discards 'const' qualifier
from pointer target type
====Signed-off-by: Alexey Brodkin
Cc: Mischa Jonker
Cc: Alim Akhtar
Cc: Rajeshwari Shinde
Cc: Jaehoon Chung
Cc: Amar
Cc: Kyungmin Park
Cc: Minkyu Kang
Cc: Simon Glass
Cc: Pantelis Antoniou
Cc: Andy Fleming -
The original codes misused recvbuf in source buffer instead of sendbuf,
and read from incorrect offset 14 instead of 22.Signed-off-by: Che-Liang Chiou
Signed-off-by: Simon Glass
Reviewed-by: Simon Glass
Tested-by: Che-Liang Chiou -
Add a simple TPM emulator for sandbox. It only supports a small subset of
TPM operations. However, these are enough to perform common tasks.Note this is an initial commit to get this working, but it could use
cleaning up (for example constants instead of open-coded values).Signed-off-by: Simon Glass
Signed-off-by: Simon Glass
Reviewed-by: Simon Glass -
Provide a way to use any host file or device as a block device in U-Boot.
This can be used to provide filesystem access within U-Boot to an ext2
image file on the host, for example.The support is plumbed into the filesystem and partition interfaces.
We don't want to print a message in the driver every time we find a missing
device. Pass the information back to the caller where a message can be printed
if desired.Signed-off-by: Henrik Nordström
Signed-off-by: Simon Glass
- Removed change to part.c get_device_and_partition()Signed-off-by: Simon Glass
Reviewed-by: Simon Glass -
To enhance the SDMMC DesignWare driver to use calloc instead of
malloc. This will avoid the incident that uninitialized members
of mmc structure are later used for NULL comparison.Signed-off-by: Chin Liang See
Cc: Rajeshwari Shinde
Cc: Jaehoon Chung
Cc: Mischa Jonker
Cc: Alexey Brodkin
Cc: Andy Fleming
Cc: Pantelis Antoniou
Acked-by: Pantelis Antoniou
08 Jan, 2014
1 commit
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The omap3_zoom2 board has not been updated for a correct CONFIG_SYS_HZ
and Tom Rix's email has long been bouncing.Signed-off-by: Tom Rini
06 Jan, 2014
1 commit
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Conflicts:
include/micrel.hThe conflict above was trivial, caused by four lines being
added in both branches with different whitepace.
03 Jan, 2014
1 commit
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Enable fuse supply before fuse programming and disable after.
Signed-off-by: Sergey Alyoshin
Reviewed-by: Benoît Thébaudeau
31 Dec, 2013
1 commit
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Fix unaligned access in OneNAND core. The problem is that the ffchars[] array
is an array of "unsigned char", but in onenand_write_ops_nolock() can be passed
to the memcpy_16() function. The memcpy_16() function will treat the buffer as
an array of "unsigned short", thus triggering unaligned access if the compiler
decided ffchars[] to be not aligned.I managed to trigger the problem with regular ELDK 5.4 GCC compiler.
Signed-off-by: Marek Vasut
Cc: Albert Aribaud
Cc: Scott Wood
Cc: Tom Rini
20 Dec, 2013
1 commit
19 Dec, 2013
10 commits
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claim spi bus while doing memory copy, this will set up
the spi controller device control register before doing
a memory read.Signed-off-by: Sourav Poddar
Tested-by: Yebio Mesfin
Reviewed-by: Jagannadha Sutradharudu Teki -
Fix the register access in EHCI HCD. We need to use address of the register
as an ehci_writel() argument.Signed-off-by: Marek Vasut
Cc: Simon Glass -
In case the controller is not initialized, we shall not de-initialize it.
As the control structure will not be filled, we will produce a null ptr
dereference if the controller is not inited.Signed-off-by: Marek Vasut
Cc: Simon Glass -
The detection function of the EHCI PCI controller was really cryptic,
add a beefy comment and clean the portion of the code up a bit. No
change in the logic of the code.Signed-off-by: Marek Vasut
Cc: Simon Glass -
Code cleanup for dfu_bind_config function
Signed-off-by: Lukasz Majewski
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It is necessary to deter the host from sending subsequent DFU_GETSTATUS
request in the case of e.g. writing the buffer to medium.Here the timeout is increased when we fill up the whole buffer. This delay
allows eMMC memory to perform its internal operations.
Otherwise we end up with HOST's error regarding GET_STATUS receive timeout.Signed-off-by: Lukasz Majewski
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The method for exporting size of allocated buffer is provided.
It is afterwards used by USB's dfu function code.Signed-off-by: Lukasz Majewski
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The RDY bit indicates that a transfer is complete. This needs to be
cleared by SW before every single HW transaction, rather than only
at the start of each SW transaction (those being made up of n HW
transactions).It seems that earlier HW may have cleared this bit autonomously when
starting a new transfer, and hence this code was not needed in practice.
However, this is generally a good idea in all cases. In Tegra124, the
HW behaviour appears to have changed, and SW must explicitly clear this
bit. Otherwise, SW will believe that transfers have completed when they
have not, and may e.g. read stale data from the RX FIFO.Signed-off-by: Yen Lin
[swarren, rewrote commit description, unified duplicate RDY clearing code
and moved it right before the start of the HW transaction, unconditionally
exit loop after reading RX data, rather than checking if TX FIFO is empty,
since it is guaranteed to be]
Signed-off-by: Stephen Warren
Reviewed-by: Jagannadha Sutradharudu Teki -
This patch adds a driver for Renesas SoC's Quad SPI bus.
This supports with 8 bits per transfer to use with SPI flash.Signed-off-by: Kouei Abe
Signed-off-by: Nobuhiro Iwamatsu
Signed-off-by: Jagannadha Sutradharudu Teki
