21 Jul, 2015
15 commits
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In case SPD address changes between board revisions, updating SPD
address can be called from board file.Signed-off-by: York Sun
Signed-off-by: Prabhakar Kushwaha -
LS2085A supports 6 personalities i.e. LS2045AE, LS2045A, LS2080AE,
LS2080A, LS2085AE and LS2085A personlities.Instead of hard-coding, board name should change as per selected
personality.Signed-off-by: Prabhakar Kushwaha
Reviewed-by: York Sun -
This patch adds support to print out the SoC personality.
Freescale LS20xx SoCs (compliant to Chassis-3 specifications) can
have 6 personalities: LS2045AE, LS2045A, LS2080AE, LS2080A,
LS2085AE and LS2085ASigned-off-by: Bhupesh Sharma
Signed-off-by: Prabhakar Kushwaha
Reviewed-by: York Sun -
DDR speed should be in MT/s, not MHz.
Signed-off-by: York Sun
Signed-off-by: Prabhakar Kushwaha -
As per updated board document, no need to substract 1 from arch[BRD]
bit field. Default value + 'A' represents the board revision.So update board version print logic to reflect the same.
Signed-off-by: Prabhakar Kushwaha
Reviewed-by: York Sun -
SYSTEM ID EPPROM always store SYSTEM version info in big endian format.
SoC with ARM or PowerPC core should read/write version info from eeprom
in BIG endian format.So use cpu-specific APIs to read SYSTEM version.
Signed-off-by: Jaiprakash Singh
Signed-off-by: Prabhakar Kushwaha
Reviewed-by: York Sun -
Increases the kernel size supported for LS2085A platforms:-
- Update environment variables
- Add ramdisk_size in bootargs env variable
- Define CONFIG_SYS_BOOTM_LEN to 64MBSigned-off-by: Bhupesh Sharma
Signed-off-by: Prabhakar Kushwaha
Reviewed-by: York Sun -
Primary Mux on I2C1 controller has slave address as 0x75.
So update its address.Signed-off-by: Prabhakar Kushwaha
Reviewed-by: York Sun -
FPGA BRDCFG9[SFP_TX] should be clear in order to enable XFI ports.
Signed-off-by: Dai Haruki
Signed-off-by: Prabhakar Kushwaha
Reviewed-by: York Sun -
call ft_pci_setup() to disable PCIe dts node if corresponding
PCIe controller is disabled according to RCWSigned-off-by: Minghuan Lian
Signed-off-by: Prabhakar Kushwaha
Reviewed-by: York Sun -
Compatible field "fsl,20851a-pcie" is not correct.
So update it to "fsl,ls2085a-pcie"Signed-off-by: Minghuan Lian
Signed-off-by: Prabhakar Kushwaha
Reviewed-by: York Sun -
SerDes Protocol 0x49 enables 4 SGMII, PEX4, SATA1 and SATA2.
Add support of 0x49 SerDes protocol to enable 4SGMII on slot4 of
ls2085aqds platform.Signed-off-by: Prabhakar Kushwaha
Reviewed-by: York Sun -
Enable "date" command for QDS and RDB boards
Signed-off-by: Priyanka Jain
Signed-off-by: Prabhakar Kushwaha
Reviewed-by: York Sun -
Add hwconfig setting for eSDHC since it shares some pins with other
IP block.Signed-off-by: Yangbo Lu
Signed-off-by: Prabhakar Kushwaha
Reviewed-by: York Sun -
Add support for board eth initialization and support for loading phy
firmware. PHY firmware needs to be loaded from board_eth_init() because
all the MACs are not initialized by ldpaa_eth driver.Signed-off-by: pankaj chauhan
Signed-off-by: Prabhakar Kushwaha
Reviewed-by: York Sun
15 Jul, 2015
25 commits
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We should not leave the expansion ROM address window open when there
is not a valid ROM.Suggested-by: Matt Porter
Signed-off-by: Bin Meng
Tested-by: Simon Glass
Acked-by: Simon Glass -
Currently PCI expansion ROM address is assigned by a call to
pciauto_setup_rom() outside of the pci auto config process.
This does not work when expansion ROM is on a device behind
PCI bridge where bridge's memory limit register was already
programmed to a value that does not cover the newly assigned
expansion ROM address. To fix this, we should configure the
ROM address during the auto config process.Signed-off-by: Bin Meng
Reviewed-by: Simon Glass
Tested-by: Simon Glass
Acked-by: Simon Glass -
This driver was originally added to support the native IDE mode for
Intel chipset, however it has some bugs like not supporting ATAPI
devices, endianness issue, or even broken build when CONFIG_LAB48.
Given no board is using this driver as of today, rather than fixing
all these issues we just remove it from the source tree.Signed-off-by: Bin Meng
Acked-by: Simon Glass -
Update crownbay_defconfig and minnowmax_defconfig with 'savedefconfig'
result so that the config option order matches Kconfig.Signed-off-by: Bin Meng
Acked-by: Simon Glass -
On 32-bit machine strtol() returns LONG_MAX which is 0x7fffffff,
which is wrong for u-boot.rom components like u-boot-x86-16bit.bin.
Change to use strtoll() so that it works on both 32-bit and 64-bit
machines.Reported-by: Fei Wang
Signed-off-by: Bin Meng
Acked-by: Simon Glass -
To try to reduce the pain of confusion of binary blobs, add MD5 checksums
for the current versions. This may worsen the situation as new versions
appear, but it should still be possible to obtain these versions, and thus
get a working setup.Signed-off-by: Simon Glass
Reviewed-by: Bin Meng -
Commit afbbd413a fixed this for non-driver-model. Make sure that the driver
model code handles this also.Signed-off-by: Simon Glass
Reviewed-by: Bin Meng -
Adjust minnowmax to use driver model for PCI. This requires adding a device
tree node to specify the ranges, removing the board-specific PCI code and
ensuring that the host bridge is configured.Reviewed-by: Bin Meng
Signed-off-by: Simon Glass -
This driver should use the x86 PCI configuration functions. Also adjust its
compatible string to something generic (i.e. without a vendor name).Signed-off-by: Simon Glass
Reviewed-by: Bin Meng -
The layout of the ROM is a bit hard to discover by reading the code. Add
a table to make it easier.Signed-off-by: Simon Glass
Reviewed-by: Bin Meng -
Enable a SPI environment and store it in a suitable place.
Signed-off-by: Simon Glass
Reviewed-by: Bin Meng
Reviewed-by: Jagan Teki -
The logic is incorrect and currently has no effect. Fix it so that we can
write to SPI flash, since by default it is write-protected.Signed-off-by: Simon Glass
Reviewed-by: Bin Meng
Tested-by: Andrew Bradford -
The status register on ICH9 is a single byte, so use byte access when
writing to it, to avoid updating the control register also.Signed-off-by: Simon Glass
Reviewed-by: Bin Meng
Reviewed-by: Jagan Teki -
Store VESA parameters to Linux setup header so that vesafb driver
in the kernel could work.Signed-off-by: Bin Meng
Acked-by: Simon Glass
Tested-by: Jian Luo -
Enable graphics support on Intel Crown Bay board With the help of
vgabios for Intel TunnelCreek IGD. Tested with an external LVDS
panel connected to X4 connector and SDVO adapter connected to X9
connector on the board.Signed-off-by: Jian Luo
Signed-off-by: Bin Meng
Acked-by: Simon Glass -
MARK_GRAPHICS_MEM_WRCOMB is not referenced anywhere in the code,
hence remove it.Signed-off-by: Bin Meng
Acked-by: Simon Glass -
Move X86_OPTION_ROM_FILE & X86_OPTION_ROM_ADDR to arch/x86/Kconfig
and rename them to VGA_BIOS_FILE & VGA_BIOS_ADDR which depend on
HAVE_VGA_BIOS. The new names are consistent with other x86 binary
blob options like HAVE_FSP/FSP_FILE/FSP_ADDR.Signed-off-by: Bin Meng
Acked-by: Simon Glass -
Print the meaningful base address and mask of an MTRR range without showing
the memory type encoding or valid bit.Signed-off-by: Bin Meng
Acked-by: Simon Glass -
Per CPUID:80000008h result, the maximum physical address bits of
TunnelCreek processor is 32 instead of default 36. This will fix
the incorrect decoding of MTRR range mask.Signed-off-by: Bin Meng
Acked-by: Simon Glass -
We should setup fixed range MTRRs for some legacy regions like VGA
RAM and PCI ROM areas as uncacheable. Note FSP may setup these to
other cache settings, but we can override this in x86_cpu_init_f().Signed-off-by: Bin Meng
Acked-by: Simon Glass -
The TunnelCreek IGD VBE reports 32-bit color depth regardless 24-bit
color depth is configured. Since 24-bit mode already uses 4 bytes
internally, it should be OK to just add this option in switch case.Signed-off-by: Jian Luo
Acked-by: Simon Glass
Tested-by: Bin Meng -
We should allow pci config read/write to host bridge (b.d.f = 0.0.0)
in the int1a_handler() which is a valid pci device.Signed-off-by: Jian Luo
Signed-off-by: Bin Meng
Acked-by: Simon Glass -
PCI option rom may use different SS during its execution, so it is not
safe to assume esp pointed to the same location in the protected mode.Signed-off-by: Jian Luo
Signed-off-by: Bin Meng
Acked-by: Simon Glass -
Per PCI spec, VGA device reports its class as standard 030000h in
its configuration space, so we can use it to determine if we need
run option rom instead of testing the supported vendor/device ids.Signed-off-by: Bin Meng
Acked-by: Simon Glass
