17 Feb, 2015
1 commit
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The value in SDRAM_REF_CTRL controls the delay time between
the initial rising edge of DDR_RESETn to rising edge of DDR_CKE
(JEDEC specs this as 500us). In order to achieve this, SDRAM_REF_CTRL
should be written with a value corresponding to 500us delay before
starting DDR initialization sequence, and configure proper
value at the end of sequence.Signed-off-by: Lokesh Vutla
16 Feb, 2015
2 commits
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The README describes the recovery method which can be used if the NAS box
is not reachable anymore. Addionally, it describes the different boot
scripts.Signed-off-by: Michael Walle
14 Feb, 2015
3 commits
13 Feb, 2015
14 commits
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G2D core should be provided 200MHz clock rate.
Signed-off-by: Joonyoung Shim
Signed-off-by: Minkyu Kang -
Some exynos boards require special handling of nRESET_OUT line for eMMC
memory to perform complete reboot e.g. Odroid X2/U3/XU3 boards.This will support eMMC reset using DT from reset_misc of samsung common
board file.Signed-off-by: Joonyoung Shim
Signed-off-by: Minkyu Kang -
Initialization of ACTLR.SMP is in lowlevel_init.
This remove duplicate function.Signed-off-by: Nobuhiro Iwamatsu
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This file was missed in the commit
https://patchwork.ozlabs.org/patch/427801/Signed-off-by: Vladimir Barinov
Signed-off-by: Nobuhiro Iwamatsu -
SILK is an entry level development board based on R-Car E2 SoC (R8A7794)
This commit supports the following peripherals:
- SCIF, I2C, Ethernet, QSPI, MMC, USB HostSigned-off-by: Vladimir Barinov
Reviewed-by: Tom Rini
Signed-off-by: Nobuhiro Iwamatsu -
Move this option to Kconfig and update all boards.
Signed-off-by: Simon Glass -
Remove driver model CONFIGs from the board config headers and use Kconfig
instead.Signed-off-by: Simon Glass
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Remove driver model CONFIGs from the board config headers and use Kconfig
instead.Signed-off-by: Simon Glass
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This also displays the "Board:" line in the bootup text with the
generic board support code.Signed-off-by: Stefan Roese
Cc: Simon Glass
Reviewed-by: Simon Glass
Signed-off-by: Simon Glass -
Adjust Kconfig to default to driver model for glacier, canyonlands and
arches.Signed-off-by: Simon Glass
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Enable CONFIG_OF_CONTROL so that U-Boot on these three boards uses a device
tree for its configuration.Signed-off-by: Simon Glass
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Add a new ramboot config for glacier so that it is possible to test U-Boot
loaded over Ethernet instead of using JTAG.Signed-off-by: Simon Glass
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Move these options to Kconfig and remove them from the CONFIG files.
Signed-off-by: Simon Glass
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Many CONFIG options have an unnecessary value of 1. CONFIG_440 is set in
the various board config files. Also simplify the CONFIG_440 check in
config.mkSigned-off-by: Simon Glass
10 Feb, 2015
8 commits
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Conflicts:
include/splash.hSigned-off-by: Tom Rini
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We now have api functions that can support compiling simplefb code as its own
module. Since this code is not part of the display functionality, extract it
to its own file.Raspberry Pi is updated to accommodate the changes.
Signed-off-by: Nikita Kiryanov
Acked-by: Stephen Warren
Reviewed-by: Simon Glass
Tested-by: Bo Shen
Tested-by: Josh Wu
Cc: Simon Glass
Cc: Anatolij Gustschin
Cc: Stephen Warren -
Currently by running the following test:
=> setenv bootcmd reset
=> save
=> reset, we observe a hang after approximately 20-30 minutes of stress reboot test.
Investigation of this issue revealed that when a single DDR chip select is used,
the hang does not happen. It only happens when the two chip selects are active.MX53 reference manual states at "28.6.2 Memory ZQ calibration sequence":
"The controller must keep the memory lines quiet (except for CK) for the ZQ
calibration time as defined in the Jedec (512 cycles for ZQCL after reset, 256
for other ZQCL and 64 for ZQCS)."According to the SDE_0 and SDE_1 bit descriptions from register ESDCTL_ESDCTL:
"Writing 1 to SDE0 or SDE1 will initiate power up delays as JEDEC defines.
Power up delays are a function of the configured memory type (DDR2/DDR3/LPDDR2)"So make sure to activate one chip select at time (CS0 first and then CS1 later),
so that the required JEDEC delay is respected for each chip select.With this change applied the board has gone through three days of reboot stress
test without any hang.Signed-off-by: Fabio Estevam
Acked-by: Stefano Babic -
Since a clock function setup_gpmi_io_clk is implemented for GPMI
IO clock settings, change to use this common function in GPMI setup.Signed-off-by: Ye.Li
Acked-by: Stefano Babic
09 Feb, 2015
3 commits
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Compile code with -fPIC to get GOT. Do not build SPL
with fPIC because it increasing SPL size for nothing.Signed-off-by: Michal Simek
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This change allows to keep board description clean and minimalistic.
This is especially helpful if one board may house different CPUs with
different features.It is applicable to both FPGA-based boards or those that have CPUs
mounted on interchnagable daughter-boards.Signed-off-by: Alexey Brodkin
08 Feb, 2015
2 commits
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Signed-off-by: Bo Shen
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The sama5d4ek support boot up from NAND flash, SD/MMC card and
also the SPI flash.Signed-off-by: Bo Shen
07 Feb, 2015
6 commits
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New board/intel/galileo board directory with minimum codes, plus
board dts, defconfig and configuration files.Signed-off-by: Bin Meng
Reviewed-by: Simon Glass
Acked-by: Simon Glass -
This is a relatively low-cost x86 board in a small form factor. The main
peripherals are uSD, USB, HDMI, Ethernet and SATA. It uses an Atom 3800
series CPU. So far only the dual core 2GB variant is supported.This uses the existing FSP support. Binary blobs are required to make this
board work. The microcode update is included as a patch (all 3000 lines of
it).Change-Id: I0088c47fe87cf08ae635b343d32c332269062156
Signed-off-by: Simon Glass
Reviewed-by: Bin Meng -
This patch fixes the following compilation warning for maxbcm:
Building maxbcm board...
text data bss dec hex filename
160075 6596 38240 204911 3206f ./u-boot
board/maxbcm/maxbcm.c: In function 'reset_phy':
board/maxbcm/maxbcm.c:68:6: warning: unused variable 'reg' [-Wunused-variable]
u16 reg;
^
board/maxbcm/maxbcm.c:66:6: warning: unused variable 'devadr' [-Wunused-variable]
u16 devadr = CONFIG_PHY_BASE_ADDR;
^Additionally support Spansion SPI NOR flash is added. With larger SPI device
support via the CONFIG_SPI_FLASH_BAR define.Signed-off-by: Stefan Roese
Reviewed-by: Luka Perkov -
This patch adds SPL support to the db-mv784mp-gp eval board.
Signed-off-by: Stefan Roese
Reviewed-by: Luka Perkov -
This patch adds SPL support to the maxbcm MV78460 based board. Including
the fixed DDR configuratrion needed for the DDR training code. And the
the serdes PHY init code.Signed-off-by: Stefan Roese
Reviewed-by: Luka Perkov -
With this patchset the Marvell bin_hdr (DDR training) code is intergrated
into mainline U-Boot. We can remove the placeholder file again, which was
only introduced to make U-Boot compile and link again.Signed-off-by: Stefan Roese
Reviewed-by: Luka Perkov
06 Feb, 2015
1 commit
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This setting will be used by more than just ivybridge so make it common.
Also rename it to PCIE_ECAM_BASE which is a more descriptive name.
Signed-off-by: Simon Glass
Reviewed-by: Bin Meng