08 Jun, 2016
1 commit
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File:
IMX6ULL_DDR3L_400MHz_1GB_16bit_V2.2.incChanges:
Change MMDC_MDMISC.WALAT to 1
setmem /32 0x021B0018 = 0x00211740Test:
Passed memtester on two mx6ull ddr3 arm2 boardsSigned-off-by: Ye Li
06 Jun, 2016
1 commit
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LCD_PWR_EN controls the G pin of Q13 PMOS which needs low voltage to connect
D to S for outputting LCD 3.3V. If LCD_PWR_EN is high, we measured the LCD 3v3
is actually 1.2V.Signed-off-by: Ye Li
(cherry picked from commit 28eb616b6c49de492cc0cdb3ad5b618bed77960f)
23 May, 2016
1 commit
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add new NAND config for i.MX6UL 14x14 EVK board, and disable USDHC2 when
NAND enabled due to pin conflict.Signed-off-by: Han Xu
(cherry picked from commit 81e175bcc07792fab6010761daf6576bd600edda)
16 May, 2016
2 commits
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Add revC board support.
Signed-off-by: Peng Fan
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In u-boot, i.MX6QP sabresd board uses 125Mhz ref clock from PHY,
While kernel uses the clock from internal PLL by setting GPR5 bit 9.
When doing warm reset in kernel, the GPR regigster is not reset, so
the clock source still is the PLL. This causes ENET in u-boot can't work.In this patch, we change the u-boot to use internal PLL to align with
kernel for i.MX6QP. This also fixes the ENET issue after kernel warm reset.Signed-off-by: Ye Li
09 May, 2016
3 commits
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On i.MX7D lpddr3, retention mode exit flow should restore
more registers to make sure the ddr controller and ddr phy
settings restored properly, otherwise, some of the boards
can NOT pass memtester after retention mode exited.For LPSR mode, ddr resume flow is same as retention mode,
just adjust it accordingly.Signed-off-by: Anson Huang
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i.MX7D TO1.2 removes the DDR PADs retention mode setting
in IOMUXC GPR, it is same as TO1.0, so only apply the
IOMUXC GPR setting for TO1.1.Signed-off-by: Anson Huang
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i.MX7D VDD_ARM/SOC standby voltage should be 0.95V,
adding 25mV margin, so set it to 0.975V;Signed-off-by: Anson Huang
04 May, 2016
1 commit
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For i.MX6QP, the QoS settings is different from others. Align with DCD.
Signed-off-by: Peng Fan
29 Apr, 2016
2 commits
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DDR script file:
arik_r2_sdb_ddr3_528_1.14.incCompass link:
http://compass.freescale.net/livelink/livelink?func=ll&objid=235302593&objAction=browse&sort=name&viewType=1Update:
setmem /32 0x020e0534 = 0x00018200 // IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR02 (SDQS0_B_TRIM=01, SDQS0_TRIM=10)
setmem /32 0x020e0538 = 0x00008000 // IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR03 (SDQS1_B_TRIM=00, SDQS1_TRIM=00)
setmem /32 0x020e053C = 0x00018200 // IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR04 (SDQS2_B_TRIM=01, SDQS2_TRIM=10)
setmem /32 0x020e0540 = 0x00018200 // IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR05 (SDQS3_B_TRIM=01, SDQS3_TRIM=10)
setmem /32 0x020e0544 = 0x00018200 // IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR06 (SDQS4_B_TRIM=01, SDQS4_TRIM=10)
setmem /32 0x020e0548 = 0x00018200 // IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR07 (SDQS5_B_TRIM=01, SDQS5_TRIM=10)
setmem /32 0x020e054C = 0x00018200 // IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR08 (SDQS6_B_TRIM=01, SDQS6_TRIM=10)
setmem /32 0x020e0550 = 0x00018200 // IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR09 (SDQS7_B_TRIM=01, SDQS7_TRIM=10)setmem /32 0x021b08c0 = 0x24912489 // fine tune SDCLK duty cyc to low - seen to improve measured duty cycle of i.mx6
setmem /32 0x021b48c0 = 0x24914452setmem /32 0x021b0018 = 0x00011740 // MMDC0_MDMISC, RALAT=0x5, WALAT=0x1
Test:
Passed stress memtester on one board.Signed-off-by: Ye Li
(cherry picked from commit b7f43f47a78c9d0c14fe104daf22efab13709ab1) -
i.MX7D TO1.2 uses same DDR script as TO1.0,
TO1.1 uses dedicated DDR script.Signed-off-by: Anson Huang
(cherry picked from commit 527d57e02b05eb0166dcaa1929e46dd2357a8720)
22 Apr, 2016
1 commit
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Since the CD pin of SD2 is DNP on the mx6ull arm2 board, this will cause
SD2 access problem even the card is inserted. Hard code the CD result to
1 to assume the card is always on.
The SD driver will return other errors if the card does not exist.Signed-off-by: Ye Li
(cherry picked from commit 47efe2fda62297ab1da8594828cd7bd928ecbda7)
21 Apr, 2016
2 commits
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1. Bind the macro CONFIG_MX6ULL_DDR3_ARM2_EMMC_REWORK to eMMC 8 bits rework, which
conflicts with QSPIA and NAND, that we have to disable them at same time.2. Bind the macro CONFIG_MX6ULL_DDR3_ARM2_QSPIB_REWORK to QSPI B port rework, which
conflicts with SD2 and NAND, that we have to disable them at same time.3. Fix a typo issue of CONFIG_MX6ULL_DDR3_ARM2_EMMC_REWORK
4. Enable QSPI support for default SD boot case.
Signed-off-by: Ye Li
(cherry picked from commit 00f36b3e9445ff47ed68262ef2d656e410cd8fcd) -
Fix build error for Plugin
"Can't stat board/freescale/mx6ul_14x14_ddr3_arm2/plugin.bin: Bad file descriptor"
Signed-off-by: Peng Fan
(cherry picked from commit 95860f1213c038ef2e5900d1874ff5398ac0be2a)
20 Apr, 2016
1 commit
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File:
IMX6ULL_DDR3L_400MHz_1GB_16bit_V2.1.incChanges:
Change ZQ_OFFSET to the default value:00
setmem /32 0x021B0890 = 0x00400000
Change IOMUXC_SW_PAD_CTL_PAD_DRAM_RESET.DDR_SEL to 11
setmem /32 0x020E0288 = 0x000C0030
Change duty cycle fine tune cell for SDCLK and SDQS
setmem /32 0x021B08C0 = 0x00944009Test:
One mx6ull ARM2 board passed memtest.Signed-off-by: Ye Li
(cherry picked from commit 8128b2f3b419a1d15a0489a91e56a4ac82eaf0c4)
13 Apr, 2016
1 commit
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Support mx6ull ddr3 arm2 board.
DDR script version 1.1. Passed memtester on 3 boards.Take mx6ul 14x14 ddr3 arm2 as reference.
Note:
LCD/NAND/ECSPI not tested, need hardware rework.Signed-off-by: Peng Fan
(cherry picked from commit 584050b98cf070bb608b652e89659ff20c47efba)
25 Mar, 2016
24 commits
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Q901 is PMOS, LCD_nPWREN should be at low voltage then output is 3V3.
If LCD_nPWREN is high, output is 2.4V which is not correct.Signed-off-by: Peng Fan
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Fix 74LV OE gpio index. pinmux is correct, but gpio index
is wrong, so gpio output will not have effect, since we
use wrong GPIO5_IO18, but not correct GPIO5_IO8.And at the end of the initialization of 74lv init, should
keep OE voltage level at LOW, but not high.Signed-off-by: Peng Fan
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Enable the configurations CONFIG_MODULE_FUSE and CONFIG_OF_SYSTEM_SETUP for
module fuse check. And modify board level codes for SD, FEC and EIM.Signed-off-by: Ye Li
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Setup MMDC in two channel fixed mode
Initialize dram banks for two channel fixed mode
DRAM bank = 0x00000000
-> start = 0x10000000
-> size = 0x20000000
DRAM bank = 0x00000001
-> start = 0x80000000
-> size = 0x20000000Signed-off-by: Adrian Alonso
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Since DDR enter retention mode after kernel enter DSM mode, we have to exit DDR
retention mode before uboot boot, so add this in DCD and plugin code.
Signed-off-by: Robin Gong
(cherry picked from commit 62248ef80dabbd7601ff4e2969368d7bf54896d9) -
Since the WDOG driver has updated to clear SRS at software assertion of
WDOG. We don't need this in board level.Signed-off-by: Ye Li
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When using watchdog timeout in kernel, the reset does not output the
WDOG_B signal, so the power supply won't be reset. To solve the problem,
we enable it in u-boot.Signed-off-by: Ye Li
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When using watchdog timeout in kernel, the reset does not output the
WDOG_B signal, so the power supply won't be reset. To solve the problem,
we enable it in u-boot.Signed-off-by: Ye Li
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Need to configure the phy AR8031 to output 125Mhz clock for ENET
reference clock. And introduce a TX clock delay.Signed-off-by: Ye Li
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Set the ID pin pad to pull up not the pull down at default, otherwise
we can't enter the device mode, but always detect as host.After this change we have to use portA cable to play as host,
and use portB cable for device.Signed-off-by: Ye.Li
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This is a demo that CM4 will boot up by u-boot without typing any
command. It boots up at u-boot early init, try to minimize the time
from power up to the CM4 running.
Since CM4 runs on QSPI NOR XIP, we have to disable the QSPI driver in
u-boot to avoid conflict.RDC for shared GPIO1 is added, but not enabled, because the kernel is
not ready for shared GPIO1. Users can uncomment the CONFIG_IMX_RDC to
enable it.Some legacy codes in mx6sxsabreauto are removed. We only need this work
on mx6sxsabresd as a demo.Signed-off-by: Ye Li
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Add board level support for android fastboot feature. Each board has
a android specified header file for defining android related configuraitons.
And add build targets for their android uboot images building.For mx6qsabreauto, mx6sabresd and mx7dsabresd, we enable the android
fastboot exclusive with DFU.Signed-off-by: Ye Li
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Integrate the FSL android fastboot features into community's fastboot.
1. Use USB gadget g_dnl driver
2. Integrate the FSL SD/SATA/NAND flash operations, since the GPT and
EFI partitions are not support by i.MX.
3. Add FDT support to community's android image.
4. Add a new boot command "boota" for android image boot. The boota
implements to load ramdisk and fdt to their loading addresses
specified in boot.img header, while bootm won't do it for android image.
5. Support the authentication of boot.img at the "load_addr" for
both SD and NAND.
6. We use new configuration CONFIG_FSL_FASTBOOT for Freescale's fastboot
with relevant header file "fsl_fastboot.h". While disabling the
configuration, the community fastboot is used.
7. Overwrite the cmdline in boot.img by using bootargs saved in local environment.
8. Add recovery and reboot-bootloader support.Signed-off-by: Ye Li
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The is_soc_rev returns true when the revision is matched, this is opposited
with uboot v2015 which returns 0. Have to fix this for mx7dsabresdSigned-off-by: Ye Li
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Modify the picosom to be suit for Brillo configurations.
Signed-off-by: Haoran Wang
(cherry picked from commit 864fd4f019674e8333b1fdb91e9242ae75f35992)
To align with 2016.03, fix several places.
Signed-off-by: Peng Fan -
Imported the picosom boot codes and board
configs from technexion.Signed-off-by: Tapani Utriainen
Signed-off-by: Haoran Wang
(cherry picked from commit d102c193f3f903055239f07ddbaab63715dbf82f) -
CONFIG_SECURE_BOOT is used for signed image building, this configuration is
not enabled at default. Comment it in board header files. Users can
uncomment it to enable.Also add CONFIG_CSF_SIZE for defining the CSF reserved size
Signed-off-by: Ye Li
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On i.MX7D TO1.1, design team adds a mux cell at the CKE path to fix the suspend
mode reset issue, but seems it add extra delay on CKE path, so CKE-CK timing violated.
When DDR enters self-refresh or retention for long time(> 15seconds per testing on some boards),
DDR data corruption occured, not able to decrease CKE delay, so we have to add extra
delay on all other signals to balance it.
DDR script needs to be fine-tuned according to this hardware change.For DDR3, since the timing margin is not good, we have to decrease the DDR frequency from
533Mhz to 400Mhz.We uses TO1.1 script at default, and retains the TO1.0 script for reference.
Compass link:
http://compass.freescale.net/livelink/livelink?func=ll&objid=235010235&objAction=browse&sort=nameSigned-off-by: Ye Li
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Porting all mx7d arm2 boards (mx7d 12x12 lpddr3, 12x12 ddr3,
19x19 ddr3, 19x19 lpddr2, 19x19 lpddr3) support from u-boot v2015.04.Signed-off-by: Ye Li
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Port LDO bypass support from v2015 to support the features:
1. Add check for 1.2GHz core speed. If Speed grading fuse is for 1.2GHz,
enable LDO bypass and setup PMIC voltages. LDO bypass is dependent
on the flatten device tree file.2. We set WDOG_B in set_anatop_bypass() before, because it is the only case, but now
on i.mx6sabreauto board, we didn't use ldo-bypass mode, but have to use WDOG_B to
reboot whole board, so split these code to independent function so that board file
can call it freely.Signed-off-by: Ye Li
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Change to use CONFIG_TARGET_MX6UL_9X9_EVK for selecting DDR script.
Signed-off-by: Ye Li
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Add support for various boot devices like NAND, QSPINOR, SPINOR,
eMMC, EIMNOR, SATA.Modify board level files to support the feature and add corresponding defconfig files
Signed-off-by: Ye Li
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Add i.MX6SX/UL arm2 boards support.
Most code are from imx_v2015.04, but adapted to 2016.03 release.Tested on mx6ul_14x14_ddr3_arm2 and mx6sx_19x19_ddr3_arm2.
Signed-off-by: Peng Fan
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Add i.MX6UL support in setup_gpmi_io_clk and change
mx6ul_14x14_evk to use it.Signed-off-by: Peng Fan
