02 Aug, 2014
2 commits
-
Implement SD driver for the S3C24xx family. This implementation
is currently only capable of using the PIO transfers, DMA is not
supported.Signed-off-by: Marek Vasut
Cc: Kyungmin Park
Cc: Lukasz Majewski
Cc: Minkyu Kang
Cc: Pantelis Antoniou
Cc: Vladimir Zapolskiy
Acked-by: Pantelis Antoniou -
Unify the register structure so they can be easily used across all
of S3C24xx lineup.Signed-off-by: Marek Vasut
Cc: Kyungmin Park
Cc: Lukasz Majewski
Cc: Minkyu Kang
Cc: Pantelis Antoniou
Cc: Vladimir Zapolskiy
Acked-by: Pantelis Antoniou
01 Aug, 2014
1 commit
-
This patch add Marvell kirkwood MVSDIO/MMC driver
and enable it for Sheevaplugs and OpenRD boards.Signed-off-by: Gerald Kerma
Reviewed-by: Stefan Roese
Acked-by: Pantelis Antoniou
31 Jul, 2014
2 commits
-
CONFIG_${CPU} is defined by Kconfig.
Signed-off-by: Masahiro Yamada
Acked-by: Simon Glass
Acked-by: Stefan Roese -
CONFIG_${ARCH} is defined by Kconfig.
Signed-off-by: Masahiro Yamada
Reviewed-by: Simon Glass
30 Jul, 2014
3 commits
-
This commit enables Kconfig.
Going forward, we use Kconfig for the board configuration.
mkconfig will never be used. Nor will include/config.mk be generated.Kconfig must be adjusted for U-Boot because our situation is
a little more complicated than Linux Kernel.
We have to generate multiple boot images (Normal, SPL, TPL)
from one source tree.
Each image needs its own configuration input.Usage:
Run "make _defconfig" to do the board configuration.
It will create the .config file and additionally spl/.config, tpl/.config
if SPL, TPL is enabled, respectively.You can use "make config", "make menuconfig" etc. to create
a new .config or modify the existing one.Use "make spl/config", "make spl/menuconfig" etc. for spl/.config
and do likewise for tpl/.config file.The generic syntax of configuration targets for SPL, TPL is:
/
Here, is either 'spl' or 'tpl'
is 'config', 'menuconfig', 'xconfig', etc.When the configuration is done, run "make".
(Or "make _defconfig all" will do the configuration and build
in one time.)For futher information of how Kconfig works in U-Boot,
please read the comment block of scripts/multiconfig.py.By the way, there is another item worth remarking here:
coexistence of Kconfig and board herder files.Prior to Kconfig, we used C headers to define a set of configs.
We expect a very long term to migrate from C headers to Kconfig.
Two different infractructure must coexist in the interim.In our former configuration scheme, include/autoconf.mk was generated
for use in makefiles.
It is still generated under include/, spl/include/, tpl/include/ directory
for the Normal, SPL, TPL image, respectively.Signed-off-by: Masahiro Yamada
Acked-by: Simon Glass -
This commit adds more Kconfig files, which were written by hand.
Signed-off-by: Masahiro Yamada
Acked-by: Simon Glass -
This commit adds:
- arch/${ARCH}/Kconfig
provide a menu to select target boards
- board/${VENDOR}/${BOARD}/Kconfig or board/${BOARD}/Kconfig
set CONFIG macros to the appropriate values for each board
- configs/${TARGET_BOARD}_defconfig
default setting of each board(This commit was automatically generated by a conversion script
based on boards.cfg)In Linux Kernel, defconfig files are located under
arch/${ARCH}/configs/ directory.
It works in Linux Kernel since ARCH is always given from the
command line for cross compile.But in U-Boot, ARCH is not given from the command line.
Which means we cannot know ARCH until the board configuration is done.
That is why all the "*_defconfig" files should be gathered into a
single directory ./configs/.Signed-off-by: Masahiro Yamada
Acked-by: Simon Glass
29 Jul, 2014
3 commits
28 Jul, 2014
14 commits
-
Having a form of whitelist to check if we know of a CPU core
and and obtain CBAR is a bit silly.It doesn't scale (how about A12, A17, as well as other I don't know
about?), and is actually a property of the SoC, not the core.So either it works and everybody is happy, or it doesn't and
the u-boot port to this SoC is providing the real address via
a configuration option.The result of the above is that this code doesn't need to exist,
is thus forcefully removed.Signed-off-by: Marc Zyngier
Acked-by: Ian Campbell -
Generate the PSCI node in the device tree.
Also add a reserve section for the "secure" code that lives in
in normal RAM, so that the kernel knows it'd better not trip on
it.Signed-off-by: Marc Zyngier
Acked-by: Ian Campbell -
Some architecture needs extra device tree setup. Instead of adding
yet another hook, convert arch_fixup_memory_node to be a generic
FDT fixup function.[maz: collapsed 3 patches into one, rewrote commit message]
Signed-off-by: Ma Haijun
Signed-off-by: Marc Zyngier
Acked-by: Ian Campbell -
Allow the switch to a second stage secure monitor just before
switching to non-secure.This allows a resident piece of firmware to be active once the
kernel has been entered (the u-boot monitor is dead anyway,
its pages being reused).Signed-off-by: Marc Zyngier
Acked-by: Ian Campbell -
Implement core support for PSCI. As this is generic code, it doesn't
implement anything really useful (all the functions are returning
Not Implemented).Signed-off-by: Marc Zyngier
Acked-by: Ian Campbell -
The current non-sec switching code suffers from one major issue:
it cannot run in secure RAM, as a large part of u-boot still needs
to be run while we're switched to non-secure.This patch reworks the whole HYP/non-secure strategy by:
- making sure the secure code is the *last* thing u-boot executes
before entering the payload
- performing an exception return from secure mode directly into
the payload
- allowing the code to be dynamically relocated to secure RAM
before switching to non-secure.This involves quite a bit of horrible code, specially as u-boot
relocation is quite primitive.Signed-off-by: Marc Zyngier
Acked-by: Ian Campbell -
In anticipation of refactoring the HYP/non-secure code to run
from secure RAM, add a new linker section that will contain that
code.Nothing is using it just yet.
Signed-off-by: Marc Zyngier
Acked-by: Ian Campbell -
In order to be able to use the various mode constants (far more
readable than random hex values), add the missing HYP and A
values.Also update arm/lib/interrupts.c to display HYP instead of an
unknown value.Signed-off-by: Marc Zyngier
Acked-by: Ian Campbell -
Before switching to non-secure, make sure that CNTVOFF is set
to zero on all CPUs. Otherwise, kernel running in non-secure
without HYP enabled (hence using virtual timers) may observe
timers that are not synchronized, effectively seeing time
going backward...Signed-off-by: Marc Zyngier
Acked-by: Ian Campbell -
A CP15 instruction execution can be reordered, requiring an
isb to be sure it is executed in program order.Signed-off-by: Marc Zyngier
Acked-by: Ian Campbell -
Having the switch to non-secure in the "prep" phase is causing
all kind of troubles, as that stage can be called multiple times.Instead, move the switch to non-secure to the last possible phase,
when there is no turning back anymore.Signed-off-by: Marc Zyngier
Acked-by: Ian Campbell
26 Jul, 2014
15 commits
-
PISMO_xx macros were used to define 'Platform Independent Storage MOdule'
related GPMC configurations. This patch
- Replaces these OMAP3 specific macros with generic CONFIG_xx macros as provided
by current u-boot infrastructure.
- Removes unused redundant macros, which are no longer required after
merging of common platform code in following commit
commit a0a37183bd75e74608bc78c8d0e2a34454f95a91
ARM: omap: merge GPMC initialization code for all platform+-----------------+-----------------------------------------------------------+
| Macro | Reason for removal |
+-----------------+-----------------------------------------------------------+
| PISMO1_NOR_BASE | duplicate of CONFIG_SYS_FLASH_BASE |
+-----------------+-----------------------------------------------------------+
| PISMO1_NAND_BASE| duplicate of CONFIG_SYS_NAND_BASE |
+-----------------+-----------------------------------------------------------+
| PISMO1_ONEN_BASE| duplicate of CONFIG_SYS_ONENAND_BASE |
+-----------------+-----------------------------------------------------------+
| PISMO1_NAND_SIZE| GPMC accesses NAND device via I/O mapped registers so |
| | configuring GPMC chip-select for smallest allowable |
| | segment (GPMC_SIZE_16M) is enough. |
+-----------------+-----------------------------------------------------------+
| PISMO1_ONEN_SIZE| OneNAND uses a fixed GPMC chip-select address-space of |
| | 128MB (GPMC_SIZE_128M) |
+-----------------+-----------------------------------------------------------+
+-----------------+-----------------------------------------------------------+
| PISMO1_NOR | Unused Macros |
| PISMO1_NAND | |
| PISMO2_CS0 | |
| PISMO2_CS1 | |
| PISMO1_ONENAND | |
| PISMO2_NAND_CS0 | |
| PISMO2_NAND_CS1 | |
| PISMO1_NOR_BASE | |
| PISMO1_NAND_BASE| |
| PISMO2_CS0_BASE | |
+-----------------+-----------------------------------------------------------+Signed-off-by: Pekon Gupta
-
Fixes commit a0a37183bd75e74608bc78c8d0e2a34454f95a91
ARM: omap: merge GPMC initialization code for all platform1) NAND device are not directly memory-mapped to CPU address-space, they are
indirectly accessed via following GPMC registers:
- GPMC_NAND_COMMAND_x
- GPMC_NAND_ADDRESS_x
- GPMC_NAND_DATA_x
Therefore from CPU's point of view, NAND address-map can be limited to just
above register addresses. But GPMC chip-select address-map can be configured
in granularity of 16MB only.
So this patch uses GPMC_SIZE_16M for all NAND devices.2) NOR device are directly memory-mapped to CPU address-space, so its
address-map size depends on actual addressable region in NOR FLASH device.
So this patch uses CONFIG_SYS_FLASH_SIZE to derive GPMC chip-select address-map
size configuration.Signed-off-by: Pekon Gupta
-
The errata is applicable on all OMAP4 (4430 and 4460/4470) and OMAP5
ES 1.0 devices. The current revision check erroneously implements this
on all DRA7 varients and with DRA722 device (which has only 1 EMIF instance)
infact causes an asynchronous abort and ends up masking it in CPSR,
only to be uncovered once the kernel switches to userspace.Signed-off-by: Rajendra Nayak
Signed-off-by: Sricharan R
Signed-off-by: Lokesh Vutla -
This patch adds Keystone2 k2e_evm evaluation board support.
Signed-off-by: Hao Zhang
Signed-off-by: Ivan Khoronzhuk -
Keystone2 K2E SoC has slightly different spl pll settings then
K2HK, so correct this.Acked-by: Murali Karicheri
Signed-off-by: Ivan Khoronzhuk -
This patch adds Keystone2 K2E SOC specific code to support
MSMC cache coherency. Also create header file for msmc to hold
its API.Acked-by: Murali Karicheri
Signed-off-by: Hao Zhang
Signed-off-by: Ivan Khoronzhuk -
This patch adds clock definitions and commands to support Keystone2
K2E SOC.Signed-off-by: Hao Zhang
Signed-off-by: Ivan Khoronzhuk -
This patch adds hardware definitions specific to Keystone II
K2E device. It has a lot common definitions with k2hk SoC, so
move them to common hardware.h. This is preparation patch for
adding K2E SoC support.Acked-by: Murali Karicheri
Signed-off-by: Hao Zhang
Signed-off-by: Ivan Khoronzhuk -
This patch in general spit SoC type clock dependent code and general
clock code. Before adding keystone II Edison k2e SoC which has
slightly different dpll set, move k2hk dependent clock code to
separate clock-k2hk.c file.Acked-by: Murali Karicheri
Signed-off-by: Ivan Khoronzhuk -
Use KS2_ prefix in all definitions, for that replace K2HK_ prefix and
add KS2_ prefix where it's needed. It requires to change names also
in places where they're used. Align lines and remove redundant
definitions in kardware-k2hk.h at the same time.Using common KS2_ prefix helps resolve redundant redefinitions and
adds opportunity to use KS2_ definition across a project not thinking about
what SoC should be used. It's more convenient and we don't need to worry
about the SoC type in common files, hardware.h will think about that.
The hardware.h decides definitions of what SoC to use.Acked-by: Murali Karicheri
Signed-off-by: Ivan Khoronzhuk -
By default all DSPs are turned off, for another case option
to turn off them is added in this commit.
Also add command to turn off itself.Acked-by: Murali Karicheri
Signed-off-by: Hao Zhang
Signed-off-by: Ivan Khoronzhuk -
The SoC related common functions in board.c should be placed to
a common keystone.c arch file.Acked-by: Murali Karicheri
Signed-off-by: Hao Zhang
Signed-off-by: Ivan Khoronzhuk -
This driver is needed in case if keystone driver is used.
Currently only keystone_net driver uses it. So to avoid
redundant code compilation make the keystone_nav dependent
on keystone net driver. It also leads to compilation errors
for boards that does't use it.Acked-by: Murali Karicheri
Signed-off-by: Ivan Khoronzhuk -
Add DDR3 PHY configs updated for PG 2.0
Also add DDR3A PHY reset before init for PG2.0 SoCs.Acked-by: Murali Karicheri
Signed-off-by: Hao Zhang
Signed-off-by: Ivan Khoronzhuk
