24 May, 2014
9 commits
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The omap_hw_init_context function (and assorted helpers) is the same for
all OMAP-derived parts as when CHSETTINGS are used, that's the same and
our DDR base is also always the same. In order to make this common we
simply need to update the names of the define for DDR address space
which is also common.Cc: Sricharan R.
Cc: Lokesh Vutla
Signed-off-by: Tom Rini
Reviewed-by: Lokesh Vutla -
Efuse register addresses are wrongly programmed.
Fixing the same.Signed-off-by: Lokesh Vutla
Acked-by: Tom Rini -
DRA72 has 1GB connected to EMIF1 only. Updating the details.
And also enable WA for BUG0039 only if corresponding EMIF is present.Signed-off-by: Lokesh Vutla
Acked-by: Tom Rini -
Adding the prcm, dplls, control module hooks for DRA72x.
Signed-off-by: Lokesh Vutla
Acked-by: Tom Rini -
TPS65917 is used in DRA722 evm. Update the address offsets accordingly.
Signed-off-by: Lokesh Vutla
Signed-off-by: Keerthy
Acked-by: Tom Rini -
Add silicon ID code for DRA722 silicon.
Signed-off-by: Lokesh Vutla
Acked-by: Tom Rini -
GPMC controller on TI's OMAP SoC is general purpose controller to interface
with different types of external devices like;
- parallel NOR flash
- parallel NAND flash
- OneNand flash
- SDR RAM
- Ethernet Devices like LAN9220Though GPMC configurations may be different for each platform depending on
clock-frequency and external device interfacing with controller. But
initialization sequence remains common across all platfoms.Thus this patch merges gpmc_init() scattered in different arch-xx/mem.c
files into single omap-common/mem-common.cHowever, actual platforms specific register config values are still sourced
from corresponding platform specific headers like;
AM33xx: arch/arm/include/asm/arch-am33xx/mem.h
OMAP3: arch/arm/include/asm/arch-omap3/mem.h
OMAP4: arch/arm/include/asm/arch-omap4/mem.h
OMAP4: arch/arm/include/asm/arch-omap5/mem.hAlso, CONFIG_xx passed by board-profile decide config for which set of macros
need to be used for initialization
CONFIG_NAND: initialize GPMC for NAND device
CONFIG_NOR: initialize GPMC for NOR device
CONFIG_ONENAND: initialize GPMC for ONENAND deviceSigned-off-by: Pekon Gupta
[trini: define GPMC_SIZE_256M for omap3]
Signed-off-by: Tom Rini -
This patch moves platform specific information for GPMC and ELM controller
into separate header files, so that any derivative devices do not mess other
header files.Platform specific information added into arch-xx/../hardware.h
- CPU related platform specific details like base-address of GPMC and ELMPlatform specific information added into arch-xx/../mem.h
- Generic configs for GPMC and ELM initialization.
- Hardware parameters or constrains specific to GPMC and ELM IP like;
number of max number of chip-selects availableSigned-off-by: Pekon Gupta
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This patch moves platform specific information for GPMC and ELM controller
into separate header files, so that any derivative devices do not mess other
header files.Platform specific information added into arch-xx/../hardware.h
- CPU related platform specific details like base-address of GPMC and ELMPlatform specific information added into arch-xx/../mem.h
- Generic configs for GPMC and ELM initialization.
- Hardware parameters or constrains specific to GPMC and ELM IP like;
number of max number of chip-selects availableSigned-off-by: Pekon Gupta
20 May, 2014
1 commit
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Conflicts:
boards.cfgConflicts were trivial once u-boot-arm/master boards.cfg was
reformatted (commit 6130c146) to match u-boot/master's own
reformatting (commit 1b37fa83).
17 May, 2014
6 commits
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P1020 SoC which has two USB controllers, but only first one is used
on this platform.Signed-off-by: Ramneek Mehresh
Reviewed-by: York Sun -
B4460 differs from B4860 only in number of CPU cores,
hence used existing support for B4860.
B4460 has 2 PPC cores whereas B4860 has 4 PPC cores.Signed-off-by: Shaveta Leekha
Signed-off-by: Sandeep Singh
Signed-off-by: Poonam Aggrwal
Reviewed-by: York Sun -
By default, all PEX inbound windows PEX_PEXIWARn[TRGT] are
mapped to 0xF, which is local memory. But for BSC9132, 0xF
is CCSR, 0x0 is local memory.Signed-off-by: Minghuan Lian
Signed-off-by: Chunhe Lan
Reviewed-by: York Sun -
Conflicts:
boards.cfgTrivial conflict, maintainer change plus board addition
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This reverts commit 258060905e04fe2eb509756ef3b37e23e220a2d6.
Conflicts:
boards.cfgWrong patch 25806090 was applied by accident. Revert it.
Signed-off-by: Masahiro Yamada
Cc: Simon Glass
Acked-by: Simon Glass
16 May, 2014
2 commits
15 May, 2014
8 commits
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Exception handling is basically identical for all ARM targets.
Factorize it out of the various start.S files and into a
single vectors.S file, and adjust linker scripts accordingly.Signed-off-by: Albert ARIBAUD
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Signed-off-by: Albert ARIBAUD
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PXA start.S has a PXA (variant) specific check in
start.S. Move it to cpuinfo.c.Signed-off-by: Albert ARIBAUD
Acked-by: Marek Vasut -
CPUs arm946es and sa1100 both define the reset_cpu()
function in their start.S file. Move this cpu-specific code
into cpu.c so that start.S only contains ARM generic code.Signed-off-by: Albert ARIBAUD
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arch/arm/cpu/arm1136/start.S contain a cache flushing function.
Remove the function and move its code into arch/arm/lib/cache.c.Signed-off-by: Albert ARIBAUD
14 May, 2014
9 commits
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Add CKOBUFFER_CLK_EN bit mask enabling FREF_XTAL_CLK clock.
Signed-off-by: Dmitry Lifshitz
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Add UART4 base address.
Signed-off-by: Dmitry Lifshitz
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Signed-off-by: Yegor Yefremov
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U-Boot on Tegra30 currently selects a main CPU frequency that cannot be
supported at all on some SKUs, and needs higher VDD_CPU/VDD_CORE values
on some others. This can result in unreliable operation of the main CPUs.Resolve this by switching to a CPU frequency that can be supported by any
SKU. According to the following link, the maximum supported CPU frequency
of the slowest Tegra30 SKU is 600MHz:repo http://nv-tegra.nvidia.com/gitweb/?p=linux-2.6.git;a=summary
branch l4t/l4t-r16-r2
path arch/arm/mach-tegra/tegra3_dvfs.c
table cpu_dvfs_table[]According to that same table, the minimum VDD_CPU required to operate at
that frequency across all SKUs is 1.007V. Given the adjustment resolution
of the TPS65911 PMIC that's used on all Tegra30-based boards we support,
we'll end up using 1.0125V instead.At that VDD_CPU, tegra3_get_core_floor_mv() in that same file dictates
that VDD_CORE must be at least 1.2V on all SKUs. According to
tegra_core_speedo_mv() (in tegra3_speedo.c in the same source tree),
that voltage is safe for all SKUs.An alternative would be to port much of the code from tegra3_dvfs.c and
tegra3_speedo.c in the kernel tree mentioned above. That's more work
than I want to take on right now.While all the currently supported boards use the same regulator chip for
VDD_CPU, different types of regulators are used for VDD_CORE. Hence, we
add some small conditional code to select how VDD_CORE is programmed. If
this becomes more complex in the future as new boards are added, or we
end up adding code to detect the SoC SKU and dynamically determine the
allowed frequency and required voltages, we should probably make this a
runtime call into a function provided by the board file and/or relevant
PMIC driver.Cc: Alban Bedel
Cc: Marcel Ziswiler
Cc: Bard Liao
Signed-off-by: Stephen Warren
Signed-off-by: Tom Warren -
The HW-defined procedure for booting Tegra requires that
CLAMP_INPUTS_WHEN_TRISTATED be enabled before programming the pinmux.
Add a function to the pinmux driver to allow boards to do this.Signed-off-by: Stephen Warren
Signed-off-by: Tom Warren -
The HW-defined procedure for booting Tegra requires that some pins be
set up as GPIOs immediately at boot in order to avoid glitches on those
pins, when the pinmux is programmed. Add a feature to the GPIO driver
which executes a GPIO configuration table. Board files will use this to
implement the correct HW initialization procedure.Signed-off-by: Stephen Warren
Signed-off-by: Tom Warren -
Define enum PMUX_FUNC_DEFAULT, which indicates that a table entry passed
to pinmux_config_pingrp()/pinmux_config_pingrp_table() shouldn't change
the mux option in HW.For pins that will be used as GPIOs, the mux option is irrelevant, so we
simply don't want to define any mux option in the pinmux initialization
table.Signed-off-by: Stephen Warren
Signed-off-by: Tom Warren -
The register writes performed by arch/arm/cpu/arm720t/tegra30/cpu.c
enable_cpu_power_rail() set the voltage to 1.0V not 1.4V as the comment
implies. Fix the comment.Signed-off-by: Stephen Warren
Signed-off-by: Tom Warren -
If CONFIG_API is ever to be enabled on Tegra, this define must be set,
since api/api_storage.c uses it.A couple of annoyting things about CONFIG_SYS_MMC_MAX_DEVICE
1) It isn't documented in README. The same is true for a lot of similar
defines used by api_storage.c.2) It doesn't represent MAX_DEVICE but rather NUM_DEVICES, since the
valid values are 0..n-1 not 0..n.However, I this patch does not address those shortcomings.
Signed-off-by: Stephen Warren
Signed-off-by: Tom Warren
13 May, 2014
5 commits
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The argument boot_flag of board_inti_f() hasn't been used for powerpc until
recent changing to use generic board. Set it to 0 as a proper value.Signed-off-by: York Sun
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baord_init_f takes one argument, boot_flag. It has not been used for
powerpc, until recently changing to use generic board architecture.
The boot flag is added as a return value from cpu_init_f().Signed-off-by: York Sun
CC: Alexander Graf -
The pointer of device tree comes from r3 for QEMU. This is not the case
for normal SoCs out of reset. Having gd->fdt_blob as 0 is important for
other functions to detect the non-existence of device tree.Signed-off-by: York Sun
CC: Alexander Graf -
We want to use the TLB mapping helpers in relocated mode as well. These helpers
need to have awareness of already occupied TLB entries. We already had them in
sync in non-relocated mode, but need to resync them when we move into relocated.Signed-off-by: Alexander Graf
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For the QEMU machine type, we can plug in either e500v2, e500mc, e5500
or e6500 style cores into the system. U-boot has to work with all of them.So avoid using HID1 which is not available on e500mc systems to make sure
we don't trap on it.Signed-off-by: Alexander Graf
