25 Jan, 2017
1 commit
23 Jan, 2017
1 commit
15 Jan, 2017
1 commit
15 Jun, 2016
1 commit
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LCD_PWR_EN controls the G pin of Q13 PMOS which needs low voltage to connect
D to S for outputting LCD 3.3V. If LCD_PWR_EN is high, we measured the LCD 3v3
is actually 1.2V.Signed-off-by: Ye Li
(cherry picked from commit 28eb616b6c49de492cc0cdb3ad5b618bed77960f)
30 May, 2016
7 commits
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The clock parent of the AHB root clock when using mux option 1
is the SYS PLL 270MHz clock. This is specified in Table 5-11
Clock Root Table of the i.MX 7Dual Applications Processor
Reference Manual.While it could be a documentation error, the 270MHz parent is
also mentioned in the boot ROM configuration in Table 6-28: The
clock is by default at 135MHz due to a POST_PODF value of 1
(=> divider of 2).Signed-off-by: Stefan Agner
(cherry picked from commit 8183b60202754d9d33ac1a2a68a5cc2cc4640fc6) -
Add revC board support.
Signed-off-by: Peng Fan
(cherry picked from commit 1f0bb3940876c9b0be6f3c5fc320dde81ced4d97)
(cherry picked from commit e28beed75d8c501777f6eeadd127b1cb601115f8) -
On i.MX7D lpddr3, retention mode exit flow should restore
more registers to make sure the ddr controller and ddr phy
settings restored properly, otherwise, some of the boards
can NOT pass memtester after retention mode exited.For LPSR mode, ddr resume flow is same as retention mode,
just adjust it accordingly.Signed-off-by: Anson Huang
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i.MX7D TO1.2 removes the DDR PADs retention mode setting
in IOMUXC GPR, it is same as TO1.0, so only apply the
IOMUXC GPR setting for TO1.1.Signed-off-by: Anson Huang
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i.MX7D VDD_ARM/SOC standby voltage should be 0.95V,
adding 25mV margin, so set it to 0.975V;Signed-off-by: Anson Huang
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Default build target supports TO1.0 and TO1.2,
TO1.1 uses its own defconfig.Signed-off-by: Anson Huang
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i.MX7D TO1.2 uses same DDR script as TO1.0,
TO1.1 uses dedicated DDR script.Signed-off-by: Anson Huang
25 May, 2016
1 commit
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…ot.img based on NAND boot. 100%
For sparse system.img, USB can trasfer system.img through spliting image into two sparse images.
For android_root.img, the second part will overwrite the first one.
It is a workaround to enlarge CONFIG_USB_FASTBOOT_BUF_SIZE to hold system image whose size is more than 400M.Signed-off-by: zhang sanshan <b51434@freescale.com>
15 Apr, 2016
1 commit
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Adjust POR_B settings on i.MX6ULL according to design
team's suggestion:2'b00 : always PUP100K
2'b01 : PUP100K when PMIC_ON_REQ || SOC_NOT_FAIL
2'b10 : always disable PUP100K
2'b11 : PDN100K when SOC_FAIL, PUP100K when SOC_NOT_FAIL -- recommended settingSigned-off-by: Anson Huang
14 Apr, 2016
1 commit
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1 Add some APIs to operate BCB/command.
2 Add action to check the command of BCB.
It can cover the case that power down when do factory-reset\ota in recovery mode.Signed-off-by: zhang sanshan
12 Apr, 2016
12 commits
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MXC_CCM_CCGR3_LDB_DI0_OFFSET should not be disabled for i.MX6SX.
Otherwise met compile error. And Discard the if else.Signed-off-by: Peng Fan
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Support mx6ull ddr3 arm2 board.
DDR script version 1.1. Passed memtester on 3 boards.Take mx6ul 14x14 ddr3 arm2 as reference.
Note:
LCD/NAND/ECSPI not tested, need hardware rework.Signed-off-by: Peng Fan
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Since the mx6ull adds the AIPS3, so enable its initialization.
Signed-off-by: Ye Li
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Update memory map address for mx6ull which uses AIPS3 and adjust UART8
to AIPS3 by replacing for ESAI.Signed-off-by: Ye Li
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Update CCM registers and clock settings according the mx6ull changes
Signed-off-by: Ye Li
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Since the work around is only for mx6ul TO1.0, so not use it for mx6ull.
Signed-off-by: Peng Fan
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The PFD reset is not needed for mx6ull, since it uses runtime cpu id
checking here, add codes to skip it.Signed-off-by: Ye Li
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The MX6ULL has GPT with supporting OSC clock source, update the driver
accordingly.Signed-off-by: Ye Li
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The MX6ULL has two 128 bits fuse banks, bank 7 and bank 8, while other
banks use 256 bits. So we have to adjust the word and bank index when accessing
the bank 8.Signed-off-by: Ye Li
Signed-off-by: Peng Fan -
Since iMX6ULL is derivative of iMX6UL, most of design are same, so enable
CONFIG_MX6UL to reduce duplicated effort.We can use CONFIG_MX6ULL for the difference between these two chips.
Signed-off-by: Ye Li
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Add MXC_CPU_MX6ULL for i.MX6ULL CPU ID
Signed-off-by: Ye Li
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Add iomux headers according the file SDK_IOMaps_i.MX6ULL_Headers_b151218.zip
Signed-off-by: Ye Li
11 Apr, 2016
2 commits
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Partition name change from slotmeta to misc.
Read/write raw data on partition misc, not use ext4 file system.Store meta in bootloader_message.slot_suffix, as defined in
bootable/recovery/bootloader.hThe first 4 bytes of boot_ctl are defined as magic number.
Also, modify code to remove warning in drivers/usb/gadget/bootctrl.c
warning: implicit declaration of function 'do_read'Signed-off-by: fang hui
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brillo need bootlader support boot control.
bootlader can choose which slot(partition) to boot based on
it's tactic.
The commit support boot control for evk6ulSigned-off-by: fang hui
30 Mar, 2016
1 commit
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provide one config "CONFIG_NAND_MXS_BCH_LEGACY_GEO" to keep using legacy
bch geometry.NOTICE: the feature must be enabled/disabled in both u-boot and kernel.
Signed-off-by: Han Xu
24 Mar, 2016
1 commit
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From TO1.1, SNVS adds internal pull up control for POR_B,
the register filed is GPBIT[1:0], after system boot up,
it can be set to 2b'01 to disable internal pull up.
It can save about 30uA power in SNVS mode.Signed-off-by: Anson Huang
15 Mar, 2016
2 commits
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Q901 is PMOS, LCD_nPWREN should be at low voltage then output is 3V3.
If LCD_nPWREN is high, output is 2.4V which is not correct.Signed-off-by: Peng Fan
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Fix 74LV OE gpio index. pinmux is correct, but gpio index
is wrong, so gpio output will not have effect, since we
use wrong GPIO5_IO18, but not correct GPIO5_IO8.And at the end of the initialization of 74lv init, should
keep OE voltage level at LOW, but not high.Signed-off-by: Peng Fan
04 Mar, 2016
8 commits
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Need the CONFIG_MX6 for using the mx6_ecspi_fused funtion, otherwise will
break build for other platforms like MX7.Signed-off-by: Ye Li
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Some type style problems found by review-commits for previous patch
MLK-12483, fix them in this patch and re-check.Signed-off-by: Ye Li
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Since the MX6UL/SL/SX only has one DDR channel, in CCM_CCDR register the bit[17]
for mmdc_ch0 is reserved and its proper state should be 1. When clear this bit,
the periph_clk_sel cannot be set and that CDHIPR[periph_clk_sel_busy] handshake
never clears.Signed-off-by: Ye Li
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Enable the configurations CONFIG_MODULE_FUSE and CONFIG_OF_SYSTEM_SETUP for
module fuse check. And modify board level codes for SD, FEC and EIM.Signed-off-by: Ye Li
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Add the fuse checking in drivers, when the module is disabled in fuse,
the driver will not work.Changed drivers: BEE, GPMI, APBH-DMA, ESDHC, FEC, QSPI, ECSPI, I2C,
USB-EHCI, GIS, LCDIF.Signed-off-by: Ye Li
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Implement a functionality to read the soc fuses and check if any module
is fused. For fused module, we have to disable it in u-boot dynamically,
and change the its node in FDT to "disabled" status before starting the kernel.In this patch, we implement the ft_system_setup for FDT fixup. This function will
be called during boot process or by "fdt systemsetup" command.To enable the module fuse checking, two configurations must be defined:
CONFIG_MODULE_FUSE
CONFIG_OF_SYSTEM_SETUPSigned-off-by: Ye Li
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When using ft_system_setup, the return value fdt_ret is not assigned,
so the fdt_strerror(fdt_ret) uses a uninitialized value.Signed-off-by: Ye Li
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The fdt command "fdt systemsetup" can't work because the do_fdt check the
start char 's' for command "fdt set". So the fdt systemsetup will also go into
the "fdt set" in fault. Fix this problem by checking the whole word "set" for
"fdt set" command.Signed-off-by: Ye Li