17 Mar, 2016

1 commit


16 Mar, 2016

4 commits


15 Mar, 2016

6 commits

  • This is based on the davinci da850evm. It can boot from either the
    on-board 16MB flash or from a microSD card. It also reads board
    information from an I2C EEPROM.

    The EV3 itself initally boots from write-protected EEPROM, so no
    u-boot SPL is needed.

    Signed-off-by: David Lechner
    Reviewed-by: Tom Rini

    David Lechner
     
  • Enable support for PMMC the TI power processor on K2G. This processor
    manages all power management related activities on the SoC and and
    allows the Operating Systems on compute processors such as ARM, DSP to
    offload the power logic away into the power processor.

    Signed-off-by: Nishanth Menon
    Reviewed-by: Tom Rini

    Nishanth Menon
     
  • There are already two FIT options in Kconfig but the CONFIG options are
    still in the header files. We need to do a proper move to fix this.

    Move these options to Kconfig and tidy up board configuration:

    CONFIG_FIT
    CONFIG_OF_BOARD_SETUP
    CONFIG_OF_SYSTEM_SETUP
    CONFIG_FIT_SIGNATURE
    CONFIG_FIT_BEST_MATCH
    CONFIG_FIT_VERBOSE
    CONFIG_OF_STDOUT_VIA_ALIAS
    CONFIG_RSA

    Unfortunately the first one is a little complicated. We need to make sure
    this option is not enabled in SPL by this change. Also this option is
    enabled automatically in the host builds by defining CONFIG_FIT in the
    image.h file. To solve this, add a new IMAGE_USE_FIT #define which can
    be used in files that are built on the host but must also build for U-Boot
    and SPL.

    Note: Masahiro's moveconfig.py script is amazing.

    Signed-off-by: Simon Glass
    [trini: Add microblaze change, various configs/ re-applies]
    Signed-off-by: Tom Rini

    Simon Glass
     
  • Move this option to Kconfig and tidy up existing boards.

    Signed-off-by: Simon Glass

    Simon Glass
     
  • Kconfig options must defined in the defconfig files. Since RSA_SOFTWARE_EXP
    relies on CONFIG_DM, unless it is set in kconfig we cannot enable RSA.
    Remove the hacks which enable CONFIG_DM in header files and update the
    defconfig.

    Signed-off-by: Simon Glass

    Simon Glass
     
  • Various boards have the wrong Kconfig ordering now. To avoid a misleading

    diff in the next patch, reorder the configuration correctly.

    Signed-off-by: Simon Glass

    Simon Glass
     

09 Mar, 2016

2 commits

  • MIPS EL boards should define CONFIG_USE_PRIVATE_LIBGCC=y to work
    with EB-only toolchains like the one from kernel.org. If one do
    not globally set CONFIG_USE_PRIVATE_LIBGCC=y, the build fails with:

    /opt/gcc-4.9.0-nolibc/mips-linux/bin/mips-linux-ld.bfd: /opt/gcc-4.9.0-nolibc/mips-linux/bin/../lib/gcc/mips-linux/4.9.0/libgcc.a(_lshrdi3.o): compiled for a big endian system and target is little endian
    /opt/gcc-4.9.0-nolibc/mips-linux/bin/mips-linux-ld.bfd: /opt/gcc-4.9.0-nolibc/mips-linux/bin/../lib/gcc/mips-linux/4.9.0/libgcc.a(_lshrdi3.o): endianness incompatible with that of the selected emulation
    /opt/gcc-4.9.0-nolibc/mips-linux/bin/mips-linux-ld.bfd: failed to merge target specific data of file /opt/gcc-4.9.0-nolibc/mips-linux/bin/../lib/gcc/mips-linux/4.9.0/libgcc.a(_lshrdi3.o)
    /opt/gcc-4.9.0-nolibc/mips-linux/bin/mips-linux-ld.bfd: /opt/gcc-4.9.0-nolibc/mips-linux/bin/../lib/gcc/mips-linux/4.9.0/libgcc.a(_ashldi3.o): compiled for a big endian system and target is little endian
    /opt/gcc-4.9.0-nolibc/mips-linux/bin/mips-linux-ld.bfd: /opt/gcc-4.9.0-nolibc/mips-linux/bin/../lib/gcc/mips-linux/4.9.0/libgcc.a(_ashldi3.o): endianness incompatible with that of the selected emulation
    /opt/gcc-4.9.0-nolibc/mips-linux/bin/mips-linux-ld.bfd: failed to merge target specific data of file /opt/gcc-4.9.0-nolibc/mips-linux/bin/../lib/gcc/mips-linux/4.9.0/libgcc.a(_ashldi3.o)
    /work/git-trees/u-boot-mips/Makefile:1171: recipe for target 'u-boot' failed

    One example for a failing build is Travis CI.

    Signed-off-by: Daniel Schwierzeck
    Reviewed-by: Purna Chandra Mandal

    Daniel Schwierzeck
     
  • - Add required UBI/UBIFS config definitions
    - Add reasonable MTD partition layout
    - Remove JFFS2 config definitions
    - Drop some CFI verbage and definitions
    - Make comment 'one-liners' truly one line
    - Improve readability and content arrangement

    Signed-off-by: Derald D. Woods
    Reviewed-by: Tom Rini

    Derald D. Woods
     

01 Mar, 2016

1 commit


29 Feb, 2016

4 commits


26 Feb, 2016

2 commits


25 Feb, 2016

9 commits


24 Feb, 2016

4 commits


23 Feb, 2016

2 commits


22 Feb, 2016

1 commit


21 Feb, 2016

4 commits

  • Tom Rini
     
  • In current design, if any peripheral was assigned to both A7 and M4,
    it will receive ipg_stop or ipg_wait when any of the 2 platforms
    enter low power mode. We will have a risk that, if A7 enter wait,
    M4 enter stop, peripheral will have chance to get ipg_stop and ipg_wait
    asserted same time. Also if M4 enters stop mode, A7 will have no
    chance to access the peripheral.
    There are 26 peripherals affected by this IC issue:
    SIM2(sim2/emvsim2)
    SIM1(sim1/emvsim1)
    UART1/UART2/UART3/UART4/UART5/UART6/UART7
    SAI1/SAI2/SAI3
    WDOG1/WDOG2/WDOG3/WDOG4
    GPT1/GPT2/GPT3/GPT4
    PWM1/PWM2/PWM3/PWM4
    ENET1/ENET2
    Software Workaround:
    The solution is to set the peripherals to Domain0 by A core, since A core
    in Domain0. The peripherals which will be used by M4, will be set to Domain1
    by M4.
    For example, A core set WDOG4 to domain0, but when M4 boots up, M4 will
    set WDOG4 to domain1, because M4 will use WDOG4.

    So the peripherals are not shared by them. This way requires
    the uboot implemented the RDC driver and set the 26 IPs above
    to domain 0 only. M4 image will set the M4 to domain 1 and
    set peripheral which it will use to domain 1.

    This patch enables the CONFIG_IMX_RDC and CONFIG_IMX_BOOTAUX for
    i.MX7D SABRESD board, and setup the 26 IP resources to domain 0.

    Signed-off-by: Ye.Li
    Signed-off-by: Peng Fan

    Peng Fan
     
  • This adds basic support to Intel Cougar Canyon 2 board, a board
    based on Chief River platform with an Ivy Bridge processor and
    a Panther Point chipset.

    Signed-off-by: Bin Meng
    Acked-by: Simon Glass

    Bin Meng
     
  • Tom Rini