05 Feb, 2021
1 commit
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The initialization of gd->arch.resv_ram pointer should depend on if the
RESV_RAM config is enabled.Signed-off-by: Hou Zhiqiang
09 Oct, 2020
1 commit
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As per hardware documentation, ECx_PMUX has precedence
over SerDes protocol.
For LX2160/LX2162 if DPMACs 17 and 18 are enabled as SGMII
through SerDes protocol but ECx_PMUX configured them as RGMII,
then the ports will be configured as RGMII and not SGMII.Signed-off-by: Razvan Ionut Cirjan
10 Sep, 2020
1 commit
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Make sure that SW_RST_REQ and RST_REQ_MSK are cleared
before triggering hardware reset request.Signed-off-by: Thirupathaiah Annapureddy
Signed-off-by: Meenakshi Aggarwal
08 Sep, 2020
1 commit
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LX2162 is LX2160 based SoC, it has same die as of LX2160
with different packaging.LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module,
microSD card, eMMC support, serial console, qspi nor flash, qsgmii,
sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes
interface to support three PCIe gen3 interface.Signed-off-by: Meenakshi Aggarwal
24 Jan, 2020
1 commit
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Exports the serdes configuration as an environment variable for LS gen 3
SoCs, so it can be used in u-boot command line. It should particularly
be useful for applying Linux DT overlays for the given serdes
configuration.
This code is called from arch_misc_init and not from the existing
serdes_init function because it depends on U-Boot environment being set
up.Signed-off-by: Alex Marginean
Reviewed-by: Priyanka Jain
18 Jan, 2020
2 commits
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At present panic() is in the vsprintf.h header file. That does not seem
like an obvious choice for hang(), even though it relates to panic(). So
let's put hang() in its own header.Signed-off-by: Simon Glass
[trini: Migrate a few more files]
Signed-off-by: Tom Rini -
These functions relate to memory init so move them into the init
header.Signed-off-by: Simon Glass
26 Dec, 2019
1 commit
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Hardware comes out of reset with implicit values, but these are outside
the accepted range for Layerscape gen 3 chassis spec used on LS1028A.
Allocate different IDs and fix up Linux DT to use them.Signed-off-by: Alex Marginean
Reviewed-by: Bin Meng
Tested-by: Michael Walle
Reviewed-by: Priyanka Jain
03 Dec, 2019
3 commits
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These functions belong in cpu_func.h since they do not use driver model.
Move them over. Don't bother adding comments since these functions should
be deleted.Signed-off-by: Simon Glass
Reviewed-by: Tom Rini -
This function belongs in mii.h so move it over.
Signed-off-by: Simon Glass
Reviewed-by: Tom Rini -
At present this function sits in its own file but it does not really
justify it. There are similar string functions in vsprintf.h, so move it
there. Also add the missing function comment.Use the vsprintf.h include file explicitly where needed.
Signed-off-by: Simon Glass
Reviewed-by: Tom Rini
08 Nov, 2019
2 commits
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While getting the 'subarg' of 'hwconfig' env variable in
config_core_prefetch(), if no hwconfig variable is defined,
below warning is received:
WARNING: Calling __hwconfig without a buffer and
before environment is readyFix this by checking 'hwconfig' env variable.
If not found return without further processing.Signed-off-by: Pankaj Bansal
Signed-off-by: Priyanka Jain
Tested-by: Michael Walle -
If the secure world reset handlers are used (via CONFIG_PSCI_RESET),
then do not use the layerscape-specific implementation.Signed-off-by: Mathew McBride
Signed-off-by: Priyanka Jain
21 Oct, 2019
1 commit
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Add LS1027A, LS1018A and LS1017A personalities support to
LS1028A SoC family.LS1028A is the prime personality of LS1028A SoC family.
LS1027A is a lower funtionality version of QorIQ LS1028A
which does not support the multimedia subsystems, such as LCD
controller, GPU, and eDP PHY.The QorIQ LS1018A and LS1017A SoCs are single 64-bit Arm A72
core, low power versions of the QorIQ LS1028A and LS1027A
SoCs respectively.Signed-off-by: Tang Yuantian
Signed-off-by: Priyanka Jain
12 Sep, 2019
1 commit
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The SP805-WDT module on LS1028A requires configuration of PMU's
PCTBENR register to enable watchdog counter decrement and reset
signal generation. The watchdog clock needs to be enabled first.Signed-off-by: Thomas Schaefer
Signed-off-by: Zhao Qiang
Reviewed-by: Priyanka Jain
12 Aug, 2019
2 commits
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This file contains lots of internal details about the environment. Most
code can include env.h instead, calling the functions there as needed.Rename this file and add a comment at the top to indicate its internal
nature.Signed-off-by: Simon Glass
Acked-by: Joe Hershberger
Reviewed-by: Simon Goldschmidt
[trini: Fixup apalis-tk1.c]
Signed-off-by: Tom Rini -
Move this function over to the new header file.
Signed-off-by: Simon Glass
Acked-by: Joe Hershberger
22 May, 2019
4 commits
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ENVL_NOWHERE is dependent on CONFIG_ENV_IS_NOWHERE and not on
CONFIG_CHAIN_OF_TRUST so return ENVL_NOWHERE when CONFIG_ENV_IS_NOWHERE
is enabledSigned-off-by: Udit Agarwal
Reviewed-by: Prabhakar Kushwaha -
Ls1028a SoC is based on Layerscape Chassis Generation 3.2
architecture with features:
2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN
ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers,
6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc.Signed-off-by: Sudhanshu Gupta
Signed-off-by: Rai Harninder
Signed-off-by: Rajesh Bhagat
Signed-off-by: Bhaskar Upadhaya
Signed-off-by: Tang Yuantian
Reviewed-by: Prabhakar Kushwaha -
The lx2160a have up to 6 PCIe controllers and have different
address and size of PCIe region.Signed-off-by: Hou Zhiqiang
Reviewed-by: Prabhakar Kushwaha -
Change to use PCIe address macro to determine if precompile the PCIe
MMU table entry.Signed-off-by: Hou Zhiqiang
Signed-off-by: Prabhakar Kushwaha
18 May, 2019
1 commit
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While converting CONFIG_SYS_[DI]CACHE_OFF to Kconfig, there are instances
where these configuration items are conditional on SPL. This commit adds SPL
variants of these configuration items, uses CONFIG_IS_ENABLED(), and updates
the configurations as required.Acked-by: Alexey Brodkin
Signed-off-by: Trevor Woerner
[trini: Make the default depend on the setting for full U-Boot, update
more zynq hardware]
Signed-off-by: Tom Rini
19 Feb, 2019
1 commit
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some dpmacs in armv8a based freescale layerscape SOCs can be
configured via both serdes(sgmii, xfi, xlaui etc) bits and via
EC*_PMUX(rgmii) bits in RCW.
e.g. dpmac 17 and 18 in LX2160A can be configured as SGMII from
serdes bits and as RGMII via EC1_PMUX/EC2_PMUX bits
Now if a dpmac is enabled by serdes bits then it takes precedence
over EC*_PMUX bits. i.e. in LX2160A if we select serdes protocol
that configures dpmac17 as SGMII and set the EC1_PMUX as RGMII,
then the dpmac is SGMII and not RGMII.Therefore, move the fsl_rgmii_init after fsl_serdes_init. in
fsl_rgmii_init function of SOC, we will check if the dpmac is enabled
or not? if it is (fsl_serdes_init has already enabled the dpmac), then
don't enable it.Signed-off-by: Pankaj Bansal
Reviewed-by: Prabhakar Kushwaha
18 Jan, 2019
2 commits
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LS1043A/LS1023A 23x23 package silicon has different SVR:VAR_PER.
Signed-off-by: Hou Zhiqiang
Reviewed-by: York Sun -
Fixes for TFABOOT framework
- update eMMC bootsrc to SD_MMC
- Increase buffer size for mcinitcmd from 256 to 512
- Fix mcinitcmd and bootcmd for Secure BootSigned-off-by: Pankit Garg
Signed-off-by: Rajesh Bhagat
Reviewed-by: York Sun
07 Dec, 2018
8 commits
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LX2160A Soc is based on Layerscape Chassis Generation 3.2
architecture with features:
16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC,
2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers,
3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs,
4 TZASC instances, etc.SoC personalites:
LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs
LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUsSigned-off-by: Bao Xiaowei
Signed-off-by: Hou Zhiqiang
Signed-off-by: Meenakshi Aggarwal
Signed-off-by: Vabhav Sharma
Signed-off-by: Sriram Dash
Signed-off-by: Priyanka Jain
Reviewed-by: York Sun -
NXP layerscape architecture Chassis 3.2 builds upon chassis3
architecture with changes like DDR Memory map change,
removal of IFC and support of upto 8 I2C controller.Patch add README.lsch3_2 and the above changes under
macro CONFIG_NXP_LSCH3_2.Signed-off-by: Sriram Dash
Signed-off-by: Priyanka Jain
Reviewed-by: York Sun -
Workaround of erratum A010539 clears the RCW source field in PORSR1
register, causing failure of detecting boot source using this method.
Use SMC call if U-Boot runs at EL2. If SMC is not implemented or
running at EL3, continue to read PORSR1 and presume QSPI as boot
source if erratum workaround A010539 is enabled and RCW source is
cleared.Signed-off-by: York Sun
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Adds SMC calls for getting DDR size and bank info for TFABOOT.
Signed-off-by: Rajesh Bhagat
Signed-off-by: Pankit Garg
Reviewed-by: York Sun -
Adds bootcmd identificaton on basis on boot source, valid
in TFABOOT configuration.Signed-off-by: Rajesh Bhagat
Signed-off-by: Pankit Garg
[YS: remove unnecessary braces]
Reviewed-by: York Sun -
PORSR register holds the cfg_rcw_src field which can be used
to identify boot source.Further, it can be used to select the environment location.
Signed-off-by: Pankit Garg
Signed-off-by: Rajesh Bhagat
[YS: fix multiple checkpatch issues]
Reviewed-by: York Sun -
Adds TFABOOT support config option and add generic code to enable
execution from DDR.Signed-off-by: York Sun
Signed-off-by: Rajesh Bhagat -
Change tlb base address from OCRAM to DDR when exception level is
less than 3.Signed-off-by: Ruchika Gupta
Signed-off-by: Pankit Garg
Reviewed-by: York Sun
05 Dec, 2018
1 commit
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Move static definitions to cpu.c file, as it doesn't allow
the cpu.h file to be included in multiple c files.Signed-off-by: York Sun
24 Sep, 2018
1 commit
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Use CONFIG_IS_ENABLED(EFI_LOADER) to avoid explicitly checking CONFIG_SPL
too. This simplifies the conditional.Signed-off-by: Stephen Warren
Signed-off-by: Alexander Graf
27 Jul, 2018
1 commit
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The include/phy.h will start including dm.h, which pulls in
linux/compat.h after the attempted redefinition in
arch/arm/include/asm/armv8/mmu.h, so move this include to allow
redefinition.Signed-off-by: Joe Hershberger
07 May, 2018
1 commit
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When U-Boot started using SPDX tags we were among the early adopters and
there weren't a lot of other examples to borrow from. So we picked the
area of the file that usually had a full license text and replaced it
with an appropriate SPDX-License-Identifier: entry. Since then, the
Linux Kernel has adopted SPDX tags and they place it as the very first
line in a file (except where shebangs are used, then it's second line)
and with slightly different comment styles than us.In part due to community overlap, in part due to better tag visibility
and in part for other minor reasons, switch over to that style.This commit changes all instances where we have a single declared
license in the tag as both the before and after are identical in tag
contents. There's also a few places where I found we did not have a tag
and have introduced one.Signed-off-by: Tom Rini
04 Apr, 2018
2 commits
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EFI_RESET_PLATFORM_SPECIFIC is one of the values that can be used for the
EFI service ResetSystem. The missing definition is added. The value has to
handled in efi_reset_system().Signed-off-by: Heinrich Schuchardt
Signed-off-by: Alexander Graf -
efi_reset_system_init provides the architecture or board specific
initialization of the EFI subsystem. Errors should be caught and
signalled by a return code.Signed-off-by: Heinrich Schuchardt
Signed-off-by: Alexander Graf
16 Jan, 2018
1 commit
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The SP805-WDT module on LS1088A requires configuration of PMU's
PCTBENR register to enable watchdog counter decrement and reset
signal generation. The watchdog clock needs to be enabled first.Signed-off-by: Zhang Ying-22455
Reviewed-by: York Sun
