03 Jan, 2014
2 commits
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CONFIG_SYS_FSL_NUM_USB_CTRLS is no longer used,
update it to new CONFIG_USB_MAX_CONTROLLER_COUNT.Signed-off-by: Shengzhou Liu
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Single-source clocking is new feature introduced in T1040.
In this mode, a single differential clock is supplied to the
DIFF_SYSCLK_P/N inputs to the processor, which in turn is
used to supply clocks to the sysclock, ddrclock and usbclock.So, both ddrclock and syclock are driven by same differential
sysclock in single-source clocking mode whereas in normal clocking
mode, generally separate DDRCLK and SYSCLK pins provides
reference clock for sysclock and ddrclockDDR_REFCLK_SEL rcw bit is used to determine DDR clock source
-If DDR_REFCLK_SEL rcw bit is 0, then DDR PLLs are driven in
normal clocking mode by DDR_Reference clock-If DDR_REFCLK_SEL rcw bit is 1, then DDR PLLs are driven in
single source clocking mode by DIFF_SYSCLKAdd code to determine ddrclock based on DDR_REFCLK_SEL rcw bit.
Signed-off-by: Poonam Aggrwal
Signed-off-by: Priyanka Jain
18 Dec, 2013
1 commit
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The SH7753 EVB board has SH7753, 512MB DDR3-SDRAM, SPI ROM,
Gigabit Ethernet, and eMMC.This patch support the following functions:
- 512MB DDR3-SDRAM, SCIF4, SPI ROM, Gigabit Ethernet, eMMCSigned-off-by: Yoshihiro Shimoda
Signed-off-by: Nobuhiro Iwamatsu
16 Dec, 2013
5 commits
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Convert like follows:
CPU mpc83xx -> CONFIG_MPC83xx
CPU mpc85xx -> CONFIG_MPC85xx
CPU mpc86xx -> CONFIG_MPC86xx
CPU mpc5xxx -> CONFIG_MPC5xxx
CPU mpc8xx -> CONFIG_8xx
CPU mpc8260 -> CONFIG_8260
CPU ppc4xx -> CONFIG_4xx
CPU x86 -> CONFIG_X86
ARCH x86 -> CONFIG_X86
ARCH powerpc -> CONFIG_PPCSigned-off-by: Masahiro Yamada
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The next version VxWorks adopts device tree (for PowerPC and ARM) as its hardware
description mechanism. For PowerPC, the boot interface conforms to
the ePAPR standard, which is:void (*kernel_entry)(ulong fdt_addr,
ulong r4 /* 0 */,
ulong r5 /* 0 */,
ulong r6 /* EPAPR_MAGIC */, ulong r7 /* IMA size */,
ulong r8 /* 0 */, ulong r9 /* 0 */)For ARM, the boot interface is:
void (*kernel_entry)(void *fdt_addr)
Signed-off-by: Miao Yan
[trini: Fix build error when !CONFIG_OF_FDT is set, typo on PowerPC,
missing extern ft_fixup_num_cores]
Signed-off-by: Tom Rini -
Signed-off-by: Sonic Zhang
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Signed-off-by: Sonic Zhang
13 Dec, 2013
4 commits
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PLATFORM_RELFLAGS += -meabi
PLATFORM_CPPFLAGS += -ffixed-r2
were defined in all arch/powerpc/${CPU}/config.mk.This commit moves them to arch/powerpc/config.mk.
Signed-off-by: Masahiro Yamada
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Cc: Marek Vasut
Signed-off-by: Tom Rini
Acked-by: Marek Vasut -
Cc: Michal Simek
Signed-off-by: Tom Rini -
Some editors such as Emacs can highlight source files.
But their parser algorithm is not perfect.If you use one double-quotation alone, some editor cannot
handle it nicely and mark source lines as a string by mistake.It is preferable to use two double-quotations as a pair.
Signed-off-by: Masahiro Yamada
12 Dec, 2013
2 commits
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The default value of CONFIG_SYS_FSL_TBCLK_DIV is 16.
So, update its value as default.
Signed-off-by: Prabhakar Kushwaha
Acked-by: York Sun -
A new valid setting case added for fman1, it uses platform frequency.
Signed-off-by: Shaohui Xie
Acked-by: York Sun
11 Dec, 2013
2 commits
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Conflicts:
board/samsung/trats2/trats2.c
include/configs/exynos5250-dt.hSigned-off-by: Tom Rini
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Conflicts:
arch/arm/cpu/armv7/rmobile/Makefile
doc/README.scrapyardNeeded manual fix:
arch/arm/cpu/armv7/omap-common/Makefile
board/compulab/cm_t335/u-boot.lds
10 Dec, 2013
3 commits
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This adds a SPI framework for people to hook up simulated SPI clients.
Signed-off-by: Mike Frysinger
Signed-off-by: Simon Glass -
The new name is longer but more clearly related to sandbox.
This is in a separate patch within the same series since some comments on the
SPI series rely on it.Signed-off-by: Simon Glass
Reviewed-by: Hung-ying Tyan
09 Dec, 2013
3 commits
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Signed-off-by: Andreas Bießmann
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In order to get the very same value for legacy pin definitions and new gpio
definitions set the legacy PIN_BASE to 0.Signed-off-by: Andreas Bießmann
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This patch define new names for GPIO pins on at91 devices. Follow up patches
will convert the whole infrastructure to use these new definitions.Signed-off-by: Andreas Bießmann
Tested-by: Bo Shen
07 Dec, 2013
2 commits
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Current LDS files /DISCARD/ a lot of sections when linking ELF
files, causing diagnostic tools such as readelf or objdump to
produce partial output. Keep all section at link stage, filter
only at objcopy time so that .bin remains minimal.Signed-off-by: Albert ARIBAUD
Reviewed-by: Benoît Thébaudeau -
The lower 5 bit of MVBAR is UNK/SBZP.
So, Monitor Vector Base Address must be 32-byte aligned.
On the other hand, the secure monitor handler does not need
32-byte alignment.This commit moves ".algin 5" directive to the correct place.
Signed-off-by: Masahiro Yamada
Cc: Andre Przywara
Acked-by: Andre Przywara
06 Dec, 2013
8 commits
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This patch change the per_clocks_enable() function used in OMAP3
code to enable peripherals clocks. Only required clock should be
activated. So if the board use the uart(x) as a console we need
to activate it. The Board's config should include define to enable
every subsystem that the board use. For a complete list
of affected peripherals, registers CM_FCLKEN_PER and CM_ICLKEN_PER
should be checked.
Right now the bootloader can enable and disable clocks for:
uart(x) using CONFIG_SYS_NS16550
gpio bank (x) using CONFIG_OMAP3_GPIO_X with X = { 2, 3, 4, 5, 6 }
i2c bus using CONFIG_DRIVER_OMAP34XX_I2C.Not required gptimer(x) and mcbsp(x) for booting are disabled by default and
are not supported by any define.
Their activation need to included in the per_clocks_enable if the
peripheral is included. Not booting board should enable the peripheral
clock connected to their driverSigned-off-by: Michael Trimarchi
Cc: Igor Grinberg
Cc: Tom Rini
Acked-by: Igor Grinberg -
This patch fix following errors and warnings
spl_boot.c: In function 'exynos_spi_copy':
spl_boot.c:111:49: error: 'CONFIG_ENV_SPI_BASE' undeclared (first use in this function)
spl_boot.c:111:49: note: each undeclared identifier is reported only once for each function it appears in
spl_boot.c:142:2: error: 'SPI_FLASH_UBOOT_POS' undeclared (first use in this function)
spl_boot.c: In function 'copy_uboot_to_ram':
spl_boot.c:189:28: warning: unused variable 'param' [-Wunused-variable]
spl_boot.c: At top level:
spl_boot.c:107:13: warning: 'exynos_spi_copy' defined but not used [-Wunused-function]Signed-off-by: Minkyu Kang
Cc: Albert ARIBAUD -
Signed-off-by: Masahiro Yamada
Signed-off-by: Sonic Zhang -
Signed-off-by: Sonic Zhang
05 Dec, 2013
8 commits
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These defines didn't use anywhere.
Signed-off-by: Jaehoon Chung
Acked-by: Alexey Brodkin
Signed-off-by: Minkyu Kang -
The "int" type is right.
Signed-off-by: Jaehoon Chung
Signed-off-by: Minkyu Kang -
MPC8349 has been using mpc85xx DDR driver through a symbolic link to
mpc85xx_ddr_gen2.c. After consolidating the drivers to a single set
under driver/ddr/fsl/, the link is replaced by referring driver
directly. We now can simply enable the macro and use the driver.
Other mpc83xx SoCs still use their own driver.Signed-off-by: York Sun
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MEM_PLL_RAT on T4240/T4160 Rev2.0 uses a value which is half of Rev1.0.
It's 12 in Rev1.0, for Rev2.0 it uses 6.Signed-off-by: Roy Zang
Signed-off-by: Shaohui Xie
Acked-by: York Sun -
In PBL RAMBOOT(SPI/SD/NAND boot) mode, CPC1 used as SRAM, should disable
CPC1 speculation and keep it till relocation. Otherwise, speculation
transactions will go to DDR controller, it will cause problem.Signed-off-by: Dave Liu
Signed-off-by: Shaohui Xie
Acked-by: York Sun -
Signed-off-by: Hardik Patel
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MSTPRI0 (Master Priority 0 Register) sits at 0x01C14110 not at
0x01C14114Signed-off-by: Viktar Palstsiuk
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This patch add the OMAP34XX_UART4 memory address
Signed-off-by: Michael Trimarchi
