25 Nov, 2019
1 commit
11 Nov, 2019
1 commit
01 Nov, 2019
1 commit
10 Apr, 2019
1 commit
-
The blob command is not working on i.MX7D, i.MX8MQ and i.MX8MM
devices.Due to different cache management it's necessary to flush dcache
range for destination address so data can be available in memory.Add necessary operations in blob_encap() and blob_decap() functions.
Signed-off-by: Breno Lima
Reviewed-by: Ye Li
(cherry picked from commit 639e5c15816c3eea0d4904a72ad175627be043d8)
09 Apr, 2019
1 commit
-
Commit 22191ac35344 ("drivers/crypto/fsl: assign job-rings to
non-TrustZone") breaks HABv4 encrypted boot support in the
following i.MX devices:- i.MX6UL
- i.MX7S
- i.MX7D
- i.MX7ULPFor preparing a HABv4 encrypted boot image it's necessary to
encapsulated the generated DEK in a blob. The blob generation
function takes into consideration the Job Ring TrustZone
ownership configuration (JROWN_NS) and can be only decapsulated
by the same configuration.The ROM code expects DEK blobs encapsulated by the Secure World
environments which commonly have JROWN_NS = 0.As U-Boot is running in Secure World we must have JROWN_NS=0
so the blobs generated by dek_blob tool can be decapsulated
by the ROM code.As NXP BSP does not requires all job-rings assigned to
non-Secure world this commit can be safely reverted.This reverts commit 22191ac353445ad8fafc5a78aefcd94e78963041.
Reviewed-by: Silvano Di Ninno
Signed-off-by: Breno Lima
(cherry picked from commit 3eebc76f5571f7ce74d385235019e8eb4a6718f6)
19 Mar, 2019
3 commits
-
After the commit b9a2a0e2e9c0 ("mmc: Add support for downgrading
HS200/HS400 to HS mode"), it add a parameter in mmc_set_card_speed()
which indicates that the HS200/HS400 to HS downgrade is happening.During the HS400 initialization, first select to HS200, and config
the related clock rate, then downgrade to HS mode. So here also need
to config the downgrade value to be true, make sure in the function
mmc_set_card_speed(), after switch to HS mode, first config the
clock rate, then read the EXT_CSD. Otherwise read EXT_CSD in HS mode
at wrong clock rate, e.g. 200MHz, may lead to uncertain result.Test on i.MX8QM MEK board, some Micron eMMC will stuck in transfer
mode in this case, and USDHC will never get data transfer complete
status, cause the uboot hang.Signed-off-by: Haibo Chen
(cherry picked from commit 0ba8e1c6efa2e9c34c9b54105d6c50ee293ec1d7) -
When using CMD6 to switch eMMC card timing from HS200/HS400 to HS/legacy,
do not poll for the completion status using CMD13, but rather wait 50mS.Once the card receives the CMD6 and starts executing it, the bus is in
undefined state until both the card finishes executing the command and
until the controller switches the bus to matching timing configuration.
During this time, it is not possible to transport any commands or data
across the bus, which includes the CMD13.Signed-off-by: Marek Vasut
Cc: Jaehoon Chung
(cherry picked from commit 5dbade95cb7ebc1f3a309b00430ebf2b466d7aba)
Signed-off-by: Haibo Chen -
The mmc_select_mode_and_width() function can be called while the card
is in HS200/HS400 mode and can be used to downgrade the card to lower
mode, e.g. HS. This is used for example by mmc_boot_part_access_chk()
which cannot access the card in HS200/HS400 mode and which is in turn
called by saveenv if env is in the MMC.In such case, forcing the card clock to legacy frequency cannot work.
Instead, the card must be switched to HS mode first, from which it can
then be reprogrammed as needed.However, this procedure needs additional code changes, since the current
implementation checks whether the card correctly switched to HS mode in
mmc_set_card_speed(). The check only expects that the card will be going
to HS mode from lower modes, not from higher modes, hence add a parameter
which indicates that the HS200/HS400 to HS downgrade is happening. This
makes the code send the switch command first, reconfigure the controller
next and finally perform the EXT_CSD readback check. The last two steps
cannot be done in reverse order as the card is already in HS mode when
the clock are being switched on the controller side.Signed-off-by: Marek Vasut
Cc: Jaehoon Chung
(cherry picked from commit 523f613609545252f08f01f346ba4b0403f78b7c)
Signed-off-by: Haibo Chen
14 Mar, 2019
3 commits
-
Fix coverity issue: CID 2970630: Resource leak (RESOURCE_LEAK)
leaked_storage: Variable cdns going out of scope leaks the storage
it points to.Memory allocated by devm_kzalloc() won't be freed automatically in
u-boot, free the memory manually here.Test: Coverity scan pass.
Change-Id: I3000a2385941cef3b8b7e01611cfdc999971a4ca
Signed-off-by: Luo Ji -
Fix coverity issue:
CID 43787: Buffer not null terminated (BUFFER_SIZE_WARNING)
buffer_size_warning: Calling strncpy with a maximum size argument
of 32 bytes on destination array sdev.name of size 32 bytes might
leave the destination string unterminated.Test: Coverity scan pass.
Change-Id: Ib10e631bab893cb9cd1484082229f806b02849ba
Signed-off-by: Luo Ji -
Fix coverity issue: CID 1477258: Uninitialized scalar variable (UNINIT)
uninit_use_in_call: Using uninitialized value txbuf when calling __fswab32.Test: Coverity scan pass.
Change-Id: If57f70c272ef49a6636a59ae3b5dcc5430fd1753
Signed-off-by: Luo Ji
12 Mar, 2019
1 commit
-
Trusty is not supported for xen so we don't need to check
the keyslot package or rollback index in spl. Reassign the
dram address for spl and u-boot to avoid conflicts.Support serial init functions to enable debug console
in spl when xen is running.Test: Boot and A/B slot switch on imx8qm_mek.
Change-Id: If6829252f1ec2e32255f951715c8747181951fd0
Signed-off-by: Ji Luo
Reviewed-by: Peng Fan
11 Mar, 2019
1 commit
-
We are currently using SC_R_LAST as a marker for imx8 power domain tree
nodes without a resource attached. This value is compiled into dtb as
part of the linux build and used by uboot.The SC_R_LAST constant changes frequently as SCFW resources are added
(by design) and every time we need to update linux and uboot headers
together or boot can fail.Fix this by replacing SC_R_LAST usage with a new constant SC_R_NONE
defined to be 0xFFF0.Signed-off-by: Leonard Crestez
Reviewed-by: Peng Fan
(cherry picked from commit 93f302a6642adedfdd6336b22d08f32284539e35)
08 Mar, 2019
1 commit
-
Currenlty U1 and U2 low power modes are allowed in device mode.
Allowing U1 and U2 low power modes during data transfers in
device mode is causing U1 exit failure on some USB3 host: which
will transite to SS.inactive instead of U0, then host will send
warm reset and ultimately result in reenumeration. This is observed
on UUU tool with some PC host. Hence disable U1 and U2 low power
modes for now.USB3 spec 7.5.10.4.2 Exit from Recovery.Configuration
The port shall transition to eSS.Inactive when the following
conditions are met:
1. Either the Ux_EXIT_TIMER or the 6-ms timer
(tRecoveryConfigurationTimeout) times out.
2. For a downstream port, the transition to Recovery is not to
attempt a Hot Reset.Signed-off-by: Li Jun
(cherry picked from commit ae0cdc741f7313398539f7b576ced73871f6cd71)
05 Mar, 2019
1 commit
-
The HDMI digital PLL, bus clock and core clock need to change to improve the
firmware loading time. The clock are now set to 800 MHz for DPLL, 200 MHz for
HDMI core, and 100 MHz for HDMI bus.Signed-off-by: Oliver Brown
04 Mar, 2019
1 commit
-
On iMX8MM, the V flag in TRISTR register only reflect the state of SNSR
value, not the calibrated TEMP value. So checking this flag is not
reliable. Per IC suggestion, change to read the TEMP/AVG_TEMP directly
and check whether it in valid range 10-125C.Signed-off-by: Ye Li
(cherry picked from commit fe41c5fa6af88cce7f5a9723c82d6ad4e61357ce)
23 Feb, 2019
1 commit
-
When the temperature is out of sensor's range, the Valid bit won't be
set in TRITSR register. So the polling loop won't go out.Change the codes to retry 10 times with 100ms interval for the Valid bit.
If the timeout, we give a warning for the invalid data.Signed-off-by: Ye Li
Reviewed-by: Bai Ping
(cherry picked from commit 7ea2168e06d4f77a872f51a167ee1ed6bf2b0632)
22 Feb, 2019
1 commit
-
Current SPL code only support ONFI-compatible NAND, porting the code
from nand_base.c to support legacy full id NAND chips, such as Toshiba
TC58NVG2S0H.Signed-off-by: Han Xu
(cherry picked from commit 4086c6b9556acbec2a8748578eb4a9e719ab4ae7)
19 Feb, 2019
3 commits
-
When we probe device with virtual i2c driver, it will definitely
fail to power up the PD. Becasue the resource is owned by M4. So
set this driver to ignore the power up resultSigned-off-by: Ye Li
(cherry picked from commit 7f753d1b5950015b11be58aa937e5c14b9f26d7a) -
If a device has relevant power domain, we will check the power up
result in probing the device. If the power up is failed, the device_probe
will return failure immediately.The only exception is the new FLAG (DM_FLAG_IGNORE_POWER_ON) is set by driver
to indicate ignore the power up result.Signed-off-by: Ye Li
(cherry picked from commit 8524ca764d8fbd05da1593abfed62bb075c50cd4) -
When fspi is assigned to M4, we have to let the fspi probe failed when
its power domain is failed to power up. Because not all devices have power
domain (for example, external devices on the board). Current checking
resource owner in power domain probe is not good, change to check it in
power on.Signed-off-by: Ye Li
(cherry picked from commit b62b82ad595a744f07306db4b88d644ae024872a)
18 Feb, 2019
3 commits
-
Add a new private flag I2C_M_SRTM_STOP(0x0200) to indicate if STOP
is needed for current message.
When reading/writing registers for slave devices, generally we have two messages,
the first message writes the register address, second message reads/writes the value.
Only the last message needs STOP. But previously M4 sends STOP for each message,
this causes some slave devices treat it as end of transfer. Then, second message won't
have any effect. To solve the problem, we introduce this private STOP flag, so M4 can
STOP according to the flag.Signed-off-by: Ye Li
Reviewed-by: Peng Fan
(cherry picked from commit e8f70409620da897917dfa29dbe65be82c9129fd) -
The HDMI digital PLL, bus clock and core clock need to change to match the
settings used by the Linux driver. This allows the SECO to start and
initialize the HDMI/DP firmware.Signed-off-by: Oliver Brown
(cherry picked from commit d2713d11afc35bc2ce546f9bd065cc7477ee65cc) -
Add firmware athentication to the hdp and hdprx load functions.
If hdp_authenticate_fw is set to yes, the hdp tx firmware is athenticated.
If hdprx_authenticate_fw is set to yes, the hdp rx firmware is athenticated.Signed-off-by: Oliver Brown
(cherry picked from commit 6c0246888012c50127b40f1ab6fa6d581f725f7a)
13 Feb, 2019
1 commit
-
As endpoint.maxpackt is set at init for super speed, we can't use it
for USB2 connection, we need use the right max packet length according
to connection speed.Signed-off-by: Li Jun
(cherry picked from commit 9c6bb3684649b4ae6f0275b5ad3799ea5c8f32df)
12 Feb, 2019
5 commits
-
If the resource is not owned by current partition, we can't power on/off
it, so we'd better return probe failure.Signed-off-by: Ye Li
(cherry picked from commit 327115c1d490d35afd94ae416ad91bebd595cfe2) -
If a pad is not owned by current partition we should not set its
pinmux.Signed-off-by: Ye Li
(cherry picked from commit 547636514f8ae8b456f2351bc84cb7fb7b5fa3f3) -
We provide override binding function, so the ARCH level can use it
to determine if it is ok to bind with lpi2c driver.Signed-off-by: Ye Li
(cherry picked from commit b19418270a3d532eacb1069606fa2ab100e04601) -
Add virtual i2c driver which replies on the VService to send SRTM i2c
messages with M4.
For each output on i2c mux, M4 side abstracts a i2c bus with special bus
id. The virtual i2c mux follows basic mux design, but uses dedicated flag
to pass the abstract bus id for the mux output to virtual i2c driver.Virtual i2c and virtual i2c mux will bind nodes with compatible string
"fsl,imx-virt-i2c" and "fsl,imx-virt-i2c-mux".To support binding local i2c driver or virtual i2c driver at runtime. We
provides a override function for the driver bind. ARCH level is responsible
to implement it.Signed-off-by: Ye Li
(cherry picked from commit 25095e9f0d9816c22da97945b66439dfa277aa2b) -
Add a common iMX MU driver in misc uclass to communicate with M4.
The MU message format is defined to use 4 words as below, the driver
will use all 4 TR/RR in MU to pass one message|WORD 0 | WORD 1 | WORD 2 | WORD 3 |
|SEQ | TYPE | PAYLOAD ADDRESS | PAYLOAD LENGTH |- SEQ:
A sequence id starts from 0 and increases for each request message- TYPE:
0x1: Request. Message sent from AP will set to this value.
0x2: Response. Message responded from M4 set to this value.
0x3: MU A side is ready.
0x4: MU B side is ready.- PAYLOAD ADDRESS:
A pointer to the memory address where the uplayer message is stored- PAYLOAD LENGTH:
The uplayer message lengthSigned-off-by: Ye Li
(cherry picked from commit aba0e51cc397e1d98be950f9c15619de06ebf782)
11 Feb, 2019
1 commit
-
The usb mass storage (f_mass_storage.c) uses fixed usb index 0,
this causes problem while CDNS3 USB controller index is 1.
Modify the API of fsg to pass the controller index.Signed-off-by: Ye Li
Reviewed-by: Jun Li
24 Jan, 2019
1 commit
-
For dual bootloader, slot selection is made at spl stage, go to
fastboot when current slot is marked as unbootable in AVB will
give the user a chance to recover current slot with fastboot
commands. But in this scenario, the device can't switch to another
bootable slot automatically when a slot is marked as unbootable.Reboot the board when current slot is marked as unbootable to make the
slot switch happen in spl.Test: Slot switch to 'b' automatically when 'a' is marked as unbootable
on imx8qxp_mek.Change-Id: I94237965970d0c17ed564cf76e08d353f7b9c047
Signed-off-by: Luo Ji
22 Jan, 2019
1 commit
-
Since imx8mm TMU needs to load some registers from fuse, this is arch
dependent operation and may vary on different platforms. So add
a interface for arch level initialization.Signed-off-by: Ye Li
21 Jan, 2019
3 commits
-
Fix some warinings as "defined but not used [-Wunused-function]".
for CAAM.Test: Build and boot on imx8qm_mek.
Change-Id: I632257615a237ca2de96937e121e7a4bcab415ce
Signed-off-by: Luo Ji -
The previous driver uses a hard coded value which generates the DSI
PHY clock can fit HX8363 WVGA screen. But when switching to new WXGA
screen which needs higher pixclock and higher DSI PHY clock, the
hard coded parameters can't work.
Change to follow kernel codes to find the best value of CM, CN, CO
parameters for DSI PHY clock to meet pixclock requirement.Signed-off-by: Ye Li
-
mx7ulp EVK B will use two mipi dsi panels, the new panel RM68200_WXGA
supports WXGA resolution.Signed-off-by: Ye Li
18 Jan, 2019
3 commits
-
Support dual bootloader feature for imx8q which uses the
container format. Move the A/B slot select and verify to
SPL stage, the bootloader rollback index will be stored
at the last 8K bytes of eMMC rpmb storage.Test: Boot and rbindex verify pass on imx8q.
Change-Id: I0a48210f65984a083037a0cd3f9558951029ed7d
Signed-off-by: Ji Luo -
The CAAM driver in u-boot will use JR0 by default, but for
imx8q, both JR0 and JR1 are assigned to SECO and A core
should never access them.
Power on the JR3 in this patchset and use it to complete
the CAAM operations for imx8q.Test: CAAM self test cases pass for imx8q.
Change-Id: Ie3d77d1f2910e7f4c257c797c12b5c8a30ad936a
Signed-off-by: Ji Luo -
Add CAAM RNG generating and BLOB encap/decap
self test cases.Test: Test cases pass on imx8qm_mek/imx6qp_sabresd.
Change-Id: I538f7b1581b36df83a3006ac133ca9e7b57ab4f0
Signed-off-by: Ji Luo
16 Jan, 2019
1 commit
-
Current MXC NAND driver uses memory BBT, it will create memory BBT in each
booting by searching bad blocks.This patch enables the flash BBT, so the NAND driver can read back Bad block
table on the flash chip to create memory BBT.Signed-off-by: Ye Li
Acked-by: Peng Fan